/*
 * Copyright (C) 2017  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef _nbio_6_1_SH_MASK_HEADER
#define _nbio_6_1_SH_MASK_HEADER


// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
//PSWUSCFG0_VENDOR_ID
#define PSWUSCFG0_VENDOR_ID__VENDOR_ID__SHIFT                                                                 0x0
#define PSWUSCFG0_VENDOR_ID__VENDOR_ID_MASK                                                                   0xFFFFL
//PSWUSCFG0_DEVICE_ID
#define PSWUSCFG0_DEVICE_ID__DEVICE_ID__SHIFT                                                                 0x0
#define PSWUSCFG0_DEVICE_ID__DEVICE_ID_MASK                                                                   0xFFFFL
//PSWUSCFG0_COMMAND
#define PSWUSCFG0_COMMAND__IO_ACCESS_EN__SHIFT                                                                0x0
#define PSWUSCFG0_COMMAND__MEM_ACCESS_EN__SHIFT                                                               0x1
#define PSWUSCFG0_COMMAND__BUS_MASTER_EN__SHIFT                                                               0x2
#define PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                            0x3
#define PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                                     0x4
#define PSWUSCFG0_COMMAND__PAL_SNOOP_EN__SHIFT                                                                0x5
#define PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                       0x6
#define PSWUSCFG0_COMMAND__AD_STEPPING__SHIFT                                                                 0x7
#define PSWUSCFG0_COMMAND__SERR_EN__SHIFT                                                                     0x8
#define PSWUSCFG0_COMMAND__FAST_B2B_EN__SHIFT                                                                 0x9
#define PSWUSCFG0_COMMAND__INT_DIS__SHIFT                                                                     0xa
#define PSWUSCFG0_COMMAND__IO_ACCESS_EN_MASK                                                                  0x0001L
#define PSWUSCFG0_COMMAND__MEM_ACCESS_EN_MASK                                                                 0x0002L
#define PSWUSCFG0_COMMAND__BUS_MASTER_EN_MASK                                                                 0x0004L
#define PSWUSCFG0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                              0x0008L
#define PSWUSCFG0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                       0x0010L
#define PSWUSCFG0_COMMAND__PAL_SNOOP_EN_MASK                                                                  0x0020L
#define PSWUSCFG0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                         0x0040L
#define PSWUSCFG0_COMMAND__AD_STEPPING_MASK                                                                   0x0080L
#define PSWUSCFG0_COMMAND__SERR_EN_MASK                                                                       0x0100L
#define PSWUSCFG0_COMMAND__FAST_B2B_EN_MASK                                                                   0x0200L
#define PSWUSCFG0_COMMAND__INT_DIS_MASK                                                                       0x0400L
//PSWUSCFG0_STATUS
#define PSWUSCFG0_STATUS__INT_STATUS__SHIFT                                                                   0x3
#define PSWUSCFG0_STATUS__CAP_LIST__SHIFT                                                                     0x4
#define PSWUSCFG0_STATUS__PCI_66_EN__SHIFT                                                                    0x5
#define PSWUSCFG0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
#define PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
#define PSWUSCFG0_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
#define PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
#define PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
#define PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
#define PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                        0xe
#define PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
#define PSWUSCFG0_STATUS__INT_STATUS_MASK                                                                     0x0008L
#define PSWUSCFG0_STATUS__CAP_LIST_MASK                                                                       0x0010L
#define PSWUSCFG0_STATUS__PCI_66_EN_MASK                                                                      0x0020L
#define PSWUSCFG0_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
#define PSWUSCFG0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
#define PSWUSCFG0_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
#define PSWUSCFG0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
#define PSWUSCFG0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
#define PSWUSCFG0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
#define PSWUSCFG0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                          0x4000L
#define PSWUSCFG0_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
//PSWUSCFG0_REVISION_ID
#define PSWUSCFG0_REVISION_ID__MINOR_REV_ID__SHIFT                                                            0x0
#define PSWUSCFG0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                            0x4
#define PSWUSCFG0_REVISION_ID__MINOR_REV_ID_MASK                                                              0x0FL
#define PSWUSCFG0_REVISION_ID__MAJOR_REV_ID_MASK                                                              0xF0L
//PSWUSCFG0_PROG_INTERFACE
#define PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                       0x0
#define PSWUSCFG0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                         0xFFL
//PSWUSCFG0_SUB_CLASS
#define PSWUSCFG0_SUB_CLASS__SUB_CLASS__SHIFT                                                                 0x0
#define PSWUSCFG0_SUB_CLASS__SUB_CLASS_MASK                                                                   0xFFL
//PSWUSCFG0_BASE_CLASS
#define PSWUSCFG0_BASE_CLASS__BASE_CLASS__SHIFT                                                               0x0
#define PSWUSCFG0_BASE_CLASS__BASE_CLASS_MASK                                                                 0xFFL
//PSWUSCFG0_CACHE_LINE
#define PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                          0x0
#define PSWUSCFG0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                            0xFFL
//PSWUSCFG0_LATENCY
#define PSWUSCFG0_LATENCY__LATENCY_TIMER__SHIFT                                                               0x0
#define PSWUSCFG0_LATENCY__LATENCY_TIMER_MASK                                                                 0xFFL
//PSWUSCFG0_HEADER
#define PSWUSCFG0_HEADER__HEADER_TYPE__SHIFT                                                                  0x0
#define PSWUSCFG0_HEADER__DEVICE_TYPE__SHIFT                                                                  0x7
#define PSWUSCFG0_HEADER__HEADER_TYPE_MASK                                                                    0x7FL
#define PSWUSCFG0_HEADER__DEVICE_TYPE_MASK                                                                    0x80L
//PSWUSCFG0_BIST
#define PSWUSCFG0_BIST__BIST_COMP__SHIFT                                                                      0x0
#define PSWUSCFG0_BIST__BIST_STRT__SHIFT                                                                      0x6
#define PSWUSCFG0_BIST__BIST_CAP__SHIFT                                                                       0x7
#define PSWUSCFG0_BIST__BIST_COMP_MASK                                                                        0x0FL
#define PSWUSCFG0_BIST__BIST_STRT_MASK                                                                        0x40L
#define PSWUSCFG0_BIST__BIST_CAP_MASK                                                                         0x80L
//PSWUSCFG0_SUB_BUS_NUMBER_LATENCY
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                  0x0
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                0x8
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                  0x10
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                      0x18
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                    0x000000FFL
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                  0x0000FF00L
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                    0x00FF0000L
#define PSWUSCFG0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                        0xFF000000L
//PSWUSCFG0_IO_BASE_LIMIT
#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                          0x0
#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                               0x4
#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                         0x8
#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                              0xc
#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                            0x000FL
#define PSWUSCFG0_IO_BASE_LIMIT__IO_BASE_MASK                                                                 0x00F0L
#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                           0x0F00L
#define PSWUSCFG0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                                0xF000L
//PSWUSCFG0_SECONDARY_STATUS
#define PSWUSCFG0_SECONDARY_STATUS__CAP_LIST__SHIFT                                                           0x4
#define PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN__SHIFT                                                          0x5
#define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
#define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                              0xe
#define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
#define PSWUSCFG0_SECONDARY_STATUS__CAP_LIST_MASK                                                             0x0010L
#define PSWUSCFG0_SECONDARY_STATUS__PCI_66_EN_MASK                                                            0x0020L
#define PSWUSCFG0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define PSWUSCFG0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
#define PSWUSCFG0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define PSWUSCFG0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define PSWUSCFG0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                0x4000L
#define PSWUSCFG0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
//PSWUSCFG0_MEM_BASE_LIMIT
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                        0x0
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                       0x4
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                       0x10
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                      0x14
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                          0x0000000FL
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                         0x0000FFF0L
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                         0x000F0000L
#define PSWUSCFG0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                        0xFFF00000L
//PSWUSCFG0_PREF_BASE_LIMIT
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                  0x0
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                 0x4
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                 0x10
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                0x14
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                    0x0000000FL
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                   0x0000FFF0L
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                   0x000F0000L
#define PSWUSCFG0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                  0xFFF00000L
//PSWUSCFG0_PREF_BASE_UPPER
#define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                     0x0
#define PSWUSCFG0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                       0xFFFFFFFFL
//PSWUSCFG0_PREF_LIMIT_UPPER
#define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                   0x0
#define PSWUSCFG0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                     0xFFFFFFFFL
//PSWUSCFG0_IO_BASE_LIMIT_HI
#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                      0x0
#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                     0x10
#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                        0x0000FFFFL
#define PSWUSCFG0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                       0xFFFF0000L
//PSWUSCFG0_CAP_PTR
#define PSWUSCFG0_CAP_PTR__CAP_PTR__SHIFT                                                                     0x0
#define PSWUSCFG0_CAP_PTR__CAP_PTR_MASK                                                                       0x000000FFL
//PSWUSCFG0_INTERRUPT_LINE
#define PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                       0x0
#define PSWUSCFG0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                         0xFFL
//PSWUSCFG0_INTERRUPT_PIN
#define PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                         0x0
#define PSWUSCFG0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                           0xFFL
//PSWUSCFG0_IRQ_BRIDGE_CNTL
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                  0x0
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                             0x1
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                              0x2
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                              0x3
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                             0x4
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                   0x5
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                 0x6
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                         0x7
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                    0x0001L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                               0x0002L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                0x0004L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                0x0008L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                               0x0010L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                     0x0020L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                   0x0040L
#define PSWUSCFG0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                           0x0080L
//EXT_BRIDGE_CNTL
#define EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                                 0x0
#define EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                                   0x01L
//PSWUSCFG0_VENDOR_CAP_LIST
#define PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                              0x0
#define PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                            0x8
#define PSWUSCFG0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                              0x10
#define PSWUSCFG0_VENDOR_CAP_LIST__CAP_ID_MASK                                                                0x000000FFL
#define PSWUSCFG0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                              0x0000FF00L
#define PSWUSCFG0_VENDOR_CAP_LIST__LENGTH_MASK                                                                0x00FF0000L
//PSWUSCFG0_ADAPTER_ID_W
#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                    0x0
#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                           0x10
#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                      0x0000FFFFL
#define PSWUSCFG0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                             0xFFFF0000L
//PSWUSCFG0_PMI_CAP_LIST
#define PSWUSCFG0_PMI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
#define PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
#define PSWUSCFG0_PMI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
#define PSWUSCFG0_PMI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
//PSWUSCFG0_PMI_CAP
#define PSWUSCFG0_PMI_CAP__VERSION__SHIFT                                                                     0x0
#define PSWUSCFG0_PMI_CAP__PME_CLOCK__SHIFT                                                                   0x3
#define PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                           0x5
#define PSWUSCFG0_PMI_CAP__AUX_CURRENT__SHIFT                                                                 0x6
#define PSWUSCFG0_PMI_CAP__D1_SUPPORT__SHIFT                                                                  0x9
#define PSWUSCFG0_PMI_CAP__D2_SUPPORT__SHIFT                                                                  0xa
#define PSWUSCFG0_PMI_CAP__PME_SUPPORT__SHIFT                                                                 0xb
#define PSWUSCFG0_PMI_CAP__VERSION_MASK                                                                       0x0007L
#define PSWUSCFG0_PMI_CAP__PME_CLOCK_MASK                                                                     0x0008L
#define PSWUSCFG0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                             0x0020L
#define PSWUSCFG0_PMI_CAP__AUX_CURRENT_MASK                                                                   0x01C0L
#define PSWUSCFG0_PMI_CAP__D1_SUPPORT_MASK                                                                    0x0200L
#define PSWUSCFG0_PMI_CAP__D2_SUPPORT_MASK                                                                    0x0400L
#define PSWUSCFG0_PMI_CAP__PME_SUPPORT_MASK                                                                   0xF800L
//PSWUSCFG0_PMI_STATUS_CNTL
#define PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                         0x0
#define PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                       0x3
#define PSWUSCFG0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                              0x8
#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                         0x9
#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                          0xd
#define PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                          0xf
#define PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                       0x16
#define PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                          0x17
#define PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                            0x18
#define PSWUSCFG0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                           0x00000003L
#define PSWUSCFG0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                         0x00000008L
#define PSWUSCFG0_PMI_STATUS_CNTL__PME_EN_MASK                                                                0x00000100L
#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                           0x00001E00L
#define PSWUSCFG0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                            0x00006000L
#define PSWUSCFG0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                            0x00008000L
#define PSWUSCFG0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                         0x00400000L
#define PSWUSCFG0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                            0x00800000L
#define PSWUSCFG0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                              0xFF000000L
//PSWUSCFG0_PCIE_CAP_LIST
#define PSWUSCFG0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                                0x0
#define PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
#define PSWUSCFG0_PCIE_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
#define PSWUSCFG0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
//PSWUSCFG0_PCIE_CAP
#define PSWUSCFG0_PCIE_CAP__VERSION__SHIFT                                                                    0x0
#define PSWUSCFG0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                                0x4
#define PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                           0x8
#define PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                            0x9
#define PSWUSCFG0_PCIE_CAP__VERSION_MASK                                                                      0x000FL
#define PSWUSCFG0_PCIE_CAP__DEVICE_TYPE_MASK                                                                  0x00F0L
#define PSWUSCFG0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                             0x0100L
#define PSWUSCFG0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                              0x3E00L
//PSWUSCFG0_DEVICE_CAP
#define PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                      0x0
#define PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                             0x3
#define PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                             0x5
#define PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                                   0x6
#define PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                                    0x9
#define PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                                 0xf
#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                                0x12
#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                                0x1a
#define PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                              0x1c
#define PSWUSCFG0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                        0x00000007L
#define PSWUSCFG0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                               0x00000018L
#define PSWUSCFG0_DEVICE_CAP__EXTENDED_TAG_MASK                                                               0x00000020L
#define PSWUSCFG0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                                     0x000001C0L
#define PSWUSCFG0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                      0x00000E00L
#define PSWUSCFG0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                                   0x00008000L
#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                                  0x03FC0000L
#define PSWUSCFG0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                                  0x0C000000L
#define PSWUSCFG0_DEVICE_CAP__FLR_CAPABLE_MASK                                                                0x10000000L
//PSWUSCFG0_DEVICE_CNTL
#define PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                             0x0
#define PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                        0x1
#define PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                            0x2
#define PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                           0x3
#define PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                          0x4
#define PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                        0x5
#define PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                         0x8
#define PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                         0x9
#define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                         0xa
#define PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                             0xb
#define PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                                   0xc
#define PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                                     0xf
#define PSWUSCFG0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                               0x0001L
#define PSWUSCFG0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                          0x0002L
#define PSWUSCFG0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                              0x0004L
#define PSWUSCFG0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                             0x0008L
#define PSWUSCFG0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                            0x0010L
#define PSWUSCFG0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                          0x00E0L
#define PSWUSCFG0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                           0x0100L
#define PSWUSCFG0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                           0x0200L
#define PSWUSCFG0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                           0x0400L
#define PSWUSCFG0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                               0x0800L
#define PSWUSCFG0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                                     0x7000L
#define PSWUSCFG0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                       0x8000L
//PSWUSCFG0_DEVICE_STATUS
#define PSWUSCFG0_DEVICE_STATUS__CORR_ERR__SHIFT                                                              0x0
#define PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                         0x1
#define PSWUSCFG0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                             0x2
#define PSWUSCFG0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                          0x3
#define PSWUSCFG0_DEVICE_STATUS__AUX_PWR__SHIFT                                                               0x4
#define PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                                     0x5
#define PSWUSCFG0_DEVICE_STATUS__CORR_ERR_MASK                                                                0x0001L
#define PSWUSCFG0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                           0x0002L
#define PSWUSCFG0_DEVICE_STATUS__FATAL_ERR_MASK                                                               0x0004L
#define PSWUSCFG0_DEVICE_STATUS__USR_DETECTED_MASK                                                            0x0008L
#define PSWUSCFG0_DEVICE_STATUS__AUX_PWR_MASK                                                                 0x0010L
#define PSWUSCFG0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                       0x0020L
//PSWUSCFG0_LINK_CAP
#define PSWUSCFG0_LINK_CAP__LINK_SPEED__SHIFT                                                                 0x0
#define PSWUSCFG0_LINK_CAP__LINK_WIDTH__SHIFT                                                                 0x4
#define PSWUSCFG0_LINK_CAP__PM_SUPPORT__SHIFT                                                                 0xa
#define PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                           0xc
#define PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                            0xf
#define PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                                     0x12
#define PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                                0x13
#define PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                                0x14
#define PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                                   0x15
#define PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                                0x16
#define PSWUSCFG0_LINK_CAP__PORT_NUMBER__SHIFT                                                                0x18
#define PSWUSCFG0_LINK_CAP__LINK_SPEED_MASK                                                                   0x0000000FL
#define PSWUSCFG0_LINK_CAP__LINK_WIDTH_MASK                                                                   0x000003F0L
#define PSWUSCFG0_LINK_CAP__PM_SUPPORT_MASK                                                                   0x00000C00L
#define PSWUSCFG0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                             0x00007000L
#define PSWUSCFG0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                              0x00038000L
#define PSWUSCFG0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                       0x00040000L
#define PSWUSCFG0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                                  0x00080000L
#define PSWUSCFG0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                                  0x00100000L
#define PSWUSCFG0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                                     0x00200000L
#define PSWUSCFG0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                                  0x00400000L
#define PSWUSCFG0_LINK_CAP__PORT_NUMBER_MASK                                                                  0xFF000000L
//PSWUSCFG0_LINK_CNTL
#define PSWUSCFG0_LINK_CNTL__PM_CONTROL__SHIFT                                                                0x0
#define PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                         0x3
#define PSWUSCFG0_LINK_CNTL__LINK_DIS__SHIFT                                                                  0x4
#define PSWUSCFG0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                              0x5
#define PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                          0x6
#define PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                             0x7
#define PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                                 0x8
#define PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                               0x9
#define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                                 0xa
#define PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                                 0xb
#define PSWUSCFG0_LINK_CNTL__PM_CONTROL_MASK                                                                  0x0003L
#define PSWUSCFG0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                           0x0008L
#define PSWUSCFG0_LINK_CNTL__LINK_DIS_MASK                                                                    0x0010L
#define PSWUSCFG0_LINK_CNTL__RETRAIN_LINK_MASK                                                                0x0020L
#define PSWUSCFG0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                            0x0040L
#define PSWUSCFG0_LINK_CNTL__EXTENDED_SYNC_MASK                                                               0x0080L
#define PSWUSCFG0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                                   0x0100L
#define PSWUSCFG0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                                 0x0200L
#define PSWUSCFG0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                                   0x0400L
#define PSWUSCFG0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                                   0x0800L
//PSWUSCFG0_LINK_STATUS
#define PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                      0x0
#define PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                                   0x4
#define PSWUSCFG0_LINK_STATUS__LINK_TRAINING__SHIFT                                                           0xb
#define PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                          0xc
#define PSWUSCFG0_LINK_STATUS__DL_ACTIVE__SHIFT                                                               0xd
#define PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                               0xe
#define PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                               0xf
#define PSWUSCFG0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                        0x000FL
#define PSWUSCFG0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                                     0x03F0L
#define PSWUSCFG0_LINK_STATUS__LINK_TRAINING_MASK                                                             0x0800L
#define PSWUSCFG0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                            0x1000L
#define PSWUSCFG0_LINK_STATUS__DL_ACTIVE_MASK                                                                 0x2000L
#define PSWUSCFG0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                                 0x4000L
#define PSWUSCFG0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                                 0x8000L
//PSWUSCFG0_DEVICE_CAP2
#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                             0x0
#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                               0x4
#define PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                                0x5
#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                              0x6
#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                              0x7
#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                              0x8
#define PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                                  0x9
#define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                               0xa
#define PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                           0xb
#define PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                      0xc
#define PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                          0x12
#define PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                            0x14
#define PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                            0x15
#define PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                                0x16
#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                               0x0000000FL
#define PSWUSCFG0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                                 0x00000010L
#define PSWUSCFG0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                                  0x00000020L
#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                                0x00000040L
#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                                0x00000080L
#define PSWUSCFG0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                                0x00000100L
#define PSWUSCFG0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                                    0x00000200L
#define PSWUSCFG0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                                 0x00000400L
#define PSWUSCFG0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                             0x00000800L
#define PSWUSCFG0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                        0x00003000L
#define PSWUSCFG0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                            0x000C0000L
#define PSWUSCFG0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                              0x00100000L
#define PSWUSCFG0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                              0x00200000L
#define PSWUSCFG0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                                  0x00C00000L
//PSWUSCFG0_DEVICE_CNTL2
#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                      0x0
#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                        0x4
#define PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                      0x5
#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                                    0x6
#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                               0x7
#define PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                                     0x8
#define PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                                  0x9
#define PSWUSCFG0_DEVICE_CNTL2__LTR_EN__SHIFT                                                                 0xa
#define PSWUSCFG0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                                0xd
#define PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                            0xf
#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                        0x000FL
#define PSWUSCFG0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                          0x0010L
#define PSWUSCFG0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                        0x0020L
#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                      0x0040L
#define PSWUSCFG0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                                 0x0080L
#define PSWUSCFG0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                       0x0100L
#define PSWUSCFG0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                                    0x0200L
#define PSWUSCFG0_DEVICE_CNTL2__LTR_EN_MASK                                                                   0x0400L
#define PSWUSCFG0_DEVICE_CNTL2__OBFF_EN_MASK                                                                  0x6000L
#define PSWUSCFG0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                              0x8000L
//PSWUSCFG0_DEVICE_STATUS2
#define PSWUSCFG0_DEVICE_STATUS2__RESERVED__SHIFT                                                             0x0
#define PSWUSCFG0_DEVICE_STATUS2__RESERVED_MASK                                                               0xFFFFL
//PSWUSCFG0_LINK_CAP2
#define PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                      0x1
#define PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                       0x8
#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                                  0x9
#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                                  0x10
#define PSWUSCFG0_LINK_CAP2__RESERVED__SHIFT                                                                  0x13
#define PSWUSCFG0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                        0x000000FEL
#define PSWUSCFG0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                         0x00000100L
#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                                    0x00000E00L
#define PSWUSCFG0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                                    0x00070000L
#define PSWUSCFG0_LINK_CAP2__RESERVED_MASK                                                                    0xFFF80000L
//PSWUSCFG0_LINK_CNTL2
#define PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                        0x0
#define PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                         0x4
#define PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                              0x5
#define PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                                    0x6
#define PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                              0x7
#define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                                     0xa
#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                           0xb
#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                                    0xc
#define PSWUSCFG0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                          0x000FL
#define PSWUSCFG0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                           0x0010L
#define PSWUSCFG0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                                0x0020L
#define PSWUSCFG0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                      0x0040L
#define PSWUSCFG0_LINK_CNTL2__XMIT_MARGIN_MASK                                                                0x0380L
#define PSWUSCFG0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                       0x0400L
#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                             0x0800L
#define PSWUSCFG0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                      0xF000L
//PSWUSCFG0_LINK_STATUS2
#define PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                                   0x0
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                                  0x1
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                            0x2
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                            0x3
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                            0x4
#define PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                              0x5
#define PSWUSCFG0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                                     0x0001L
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                                    0x0002L
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                              0x0004L
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                              0x0008L
#define PSWUSCFG0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                              0x0010L
#define PSWUSCFG0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                                0x0020L
//PSWUSCFG0_MSI_CAP_LIST
#define PSWUSCFG0_MSI_CAP_LIST__CAP_ID__SHIFT                                                                 0x0
#define PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                               0x8
#define PSWUSCFG0_MSI_CAP_LIST__CAP_ID_MASK                                                                   0x00FFL
#define PSWUSCFG0_MSI_CAP_LIST__NEXT_PTR_MASK                                                                 0xFF00L
//PSWUSCFG0_MSI_MSG_CNTL
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                                 0x0
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                          0x1
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                           0x4
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                              0x7
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                              0x8
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_EN_MASK                                                                   0x0001L
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                            0x000EL
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                             0x0070L
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                                0x0080L
#define PSWUSCFG0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                                0x0100L
//PSWUSCFG0_MSI_MSG_ADDR_LO
#define PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                                     0x2
#define PSWUSCFG0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                       0xFFFFFFFCL
//PSWUSCFG0_MSI_MSG_ADDR_HI
#define PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                                     0x0
#define PSWUSCFG0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                       0xFFFFFFFFL
//PSWUSCFG0_MSI_MSG_DATA
#define PSWUSCFG0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                               0x0
#define PSWUSCFG0_MSI_MSG_DATA__MSI_DATA_MASK                                                                 0x0000FFFFL
//PSWUSCFG0_MSI_MSG_DATA_64
#define PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                         0x0
#define PSWUSCFG0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                           0xFFFFL
//PSWUSCFG0_SSID_CAP_LIST
#define PSWUSCFG0_SSID_CAP_LIST__CAP_ID__SHIFT                                                                0x0
#define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                              0x8
#define PSWUSCFG0_SSID_CAP_LIST__CAP_ID_MASK                                                                  0x00FFL
#define PSWUSCFG0_SSID_CAP_LIST__NEXT_PTR_MASK                                                                0xFF00L
//PSWUSCFG0_SSID_CAP
#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                        0x0
#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                               0x10
#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                          0x0000FFFFL
#define PSWUSCFG0_SSID_CAP__SUBSYSTEM_ID_MASK                                                                 0xFFFF0000L
//MSI_MAP_CAP_LIST
#define MSI_MAP_CAP_LIST__CAP_ID__SHIFT                                                                       0x0
#define MSI_MAP_CAP_LIST__NEXT_PTR__SHIFT                                                                     0x8
#define MSI_MAP_CAP_LIST__CAP_ID_MASK                                                                         0x00FFL
#define MSI_MAP_CAP_LIST__NEXT_PTR_MASK                                                                       0xFF00L
//MSI_MAP_CAP
#define MSI_MAP_CAP__EN__SHIFT                                                                                0x0
#define MSI_MAP_CAP__FIXD__SHIFT                                                                              0x1
#define MSI_MAP_CAP__CAP_TYPE__SHIFT                                                                          0xb
#define MSI_MAP_CAP__EN_MASK                                                                                  0x0001L
#define MSI_MAP_CAP__FIXD_MASK                                                                                0x0002L
#define MSI_MAP_CAP__CAP_TYPE_MASK                                                                            0xF800L
//MSI_MAP_ADDR_LO
#define MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO__SHIFT                                                               0x14
#define MSI_MAP_ADDR_LO__MSI_MAP_ADDR_LO_MASK                                                                 0xFFF00000L
//MSI_MAP_ADDR_HI
#define MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI__SHIFT                                                               0x0
#define MSI_MAP_ADDR_HI__MSI_MAP_ADDR_HI_MASK                                                                 0xFFFFFFFFL
//PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                                    0x0
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                                   0x10
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                                0x14
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                      0x0000FFFFL
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                                     0x000F0000L
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                                  0xFFF00000L
//PSWUSCFG0_PCIE_VENDOR_SPECIFIC1
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                       0x0
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                         0xFFFFFFFFL
//PSWUSCFG0_PCIE_VENDOR_SPECIFIC2
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                       0x0
#define PSWUSCFG0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                         0xFFFFFFFFL
//PSWUSCFG0_PCIE_VC_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
#define PSWUSCFG0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
//PSWUSCFG0_PCIE_PORT_VC_CAP_REG1
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                                  0x0
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                                     0x4
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                       0x8
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                                     0xa
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                                    0x00000007L
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                       0x00000070L
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                         0x00000300L
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                       0x00000C00L
//PSWUSCFG0_PCIE_PORT_VC_CAP_REG2
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                                    0x0
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                           0x18
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                      0x000000FFL
#define PSWUSCFG0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                             0xFF000000L
//PSWUSCFG0_PCIE_PORT_VC_CNTL
#define PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                                 0x0
#define PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                                     0x1
#define PSWUSCFG0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                                   0x0001L
#define PSWUSCFG0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                       0x000EL
//PSWUSCFG0_PCIE_PORT_VC_STATUS
#define PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                             0x0
#define PSWUSCFG0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                               0x0001L
//PSWUSCFG0_PCIE_VC0_RESOURCE_CAP
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x003F0000L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
//PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
//PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS
#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
#define PSWUSCFG0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
//PSWUSCFG0_PCIE_VC1_RESOURCE_CAP
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                                  0x0
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                            0xf
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                                0x10
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                         0x18
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                                    0x000000FFL
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                              0x00008000L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                                  0x003F0000L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                           0xFF000000L
//PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                                0x0
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                              0x1
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                          0x10
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                              0x11
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                        0x18
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                                    0x1f
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                                  0x00000001L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                                0x000000FEL
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                            0x00010000L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                                0x000E0000L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                          0x07000000L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                      0x80000000L
//PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS
#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                      0x0
#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                                     0x1
#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                        0x0001L
#define PSWUSCFG0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                       0x0002L
//PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
//PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                            0x0
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                              0xFFFFFFFFL
//PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                            0x0
#define PSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                              0xFFFFFFFFL
//PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define PSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//PSWUSCFG0_PCIE_UNCORR_ERR_STATUS
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                               0x4
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                            0x5
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                               0xc
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                                0xd
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                           0xe
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                         0xf
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                             0x10
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                              0x11
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                               0x12
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                              0x13
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                        0x14
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                         0x15
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                        0x16
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                        0x17
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                               0x18
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                                0x19
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                           0x1a
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                                 0x00000010L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                              0x00000020L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                                 0x00001000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                                  0x00002000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                             0x00004000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                           0x00008000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                               0x00010000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                                0x00020000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                                 0x00040000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                                0x00080000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                          0x00100000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                           0x00200000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                          0x00400000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                          0x00800000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                                 0x01000000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                                  0x02000000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                             0x04000000L
//PSWUSCFG0_PCIE_UNCORR_ERR_MASK
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                                   0x4
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                                0x5
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                                   0xc
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                                    0xd
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                               0xe
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                             0xf
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                                 0x10
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                                  0x11
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                                   0x12
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                                  0x13
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                            0x14
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                             0x15
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                            0x16
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                            0x17
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                                   0x18
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                                    0x19
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                               0x1a
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                                     0x00000010L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                                  0x00000020L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                                     0x00001000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                      0x00002000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                                 0x00004000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                               0x00008000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                                   0x00010000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                                    0x00020000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                                     0x00040000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                                    0x00080000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                              0x00100000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                               0x00200000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                              0x00400000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                              0x00800000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                                     0x01000000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                      0x02000000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                                 0x04000000L
//PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                           0x4
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                        0x5
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                           0xc
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                            0xd
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                       0xe
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                                     0xf
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                         0x10
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                          0x11
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                           0x12
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                          0x13
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                                    0x14
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                                     0x15
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                                    0x16
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                                    0x17
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                           0x18
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                            0x19
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                       0x1a
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                             0x00000010L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                          0x00000020L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                             0x00001000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                              0x00002000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                         0x00004000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                       0x00008000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                           0x00010000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                            0x00020000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                             0x00040000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                            0x00080000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                      0x00100000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                       0x00200000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                      0x00400000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                      0x00800000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                             0x01000000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                              0x02000000L
#define PSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                         0x04000000L
//PSWUSCFG0_PCIE_CORR_ERR_STATUS
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                                 0x0
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                                 0x6
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                                0x7
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                                     0x8
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                                    0xc
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                                   0xd
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                            0xe
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                            0xf
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                                   0x00000001L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                                   0x00000040L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                                  0x00000080L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                       0x00000100L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                      0x00001000L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                                     0x00002000L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                              0x00004000L
#define PSWUSCFG0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                              0x00008000L
//PSWUSCFG0_PCIE_CORR_ERR_MASK
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                                     0x0
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                                     0x6
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                                    0x7
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                         0x8
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                        0xc
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                       0xd
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                                0xe
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                                0xf
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                       0x00000001L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                       0x00000040L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                      0x00000080L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                           0x00000100L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                          0x00001000L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                         0x00002000L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                                  0x00004000L
#define PSWUSCFG0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                                  0x00008000L
//PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                                 0x0
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                                  0x5
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                                   0x6
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                                0x7
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                                 0x8
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                            0x9
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                             0xa
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                        0xb
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                                   0x0000001FL
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                                    0x00000020L
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                                     0x00000040L
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                                  0x00000080L
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                                   0x00000100L
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                              0x00000200L
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                               0x00000400L
#define PSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                          0x00000800L
//PSWUSCFG0_PCIE_HDR_LOG0
#define PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                               0x0
#define PSWUSCFG0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                                 0xFFFFFFFFL
//PSWUSCFG0_PCIE_HDR_LOG1
#define PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                               0x0
#define PSWUSCFG0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                                 0xFFFFFFFFL
//PSWUSCFG0_PCIE_HDR_LOG2
#define PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                               0x0
#define PSWUSCFG0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                                 0xFFFFFFFFL
//PSWUSCFG0_PCIE_HDR_LOG3
#define PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                               0x0
#define PSWUSCFG0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                                 0xFFFFFFFFL
//PSWUSCFG0_PCIE_TLP_PREFIX_LOG0
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                                     0x0
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
//PSWUSCFG0_PCIE_TLP_PREFIX_LOG1
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                                     0x0
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
//PSWUSCFG0_PCIE_TLP_PREFIX_LOG2
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                                     0x0
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
//PSWUSCFG0_PCIE_TLP_PREFIX_LOG3
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                                     0x0
#define PSWUSCFG0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                       0xFFFFFFFFL
//PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
#define PSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
//PSWUSCFG0_PCIE_LINK_CNTL3
#define PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                                0x0
#define PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                        0x1
#define PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                             0x9
#define PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                            0x10
#define PSWUSCFG0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                                  0x00000001L
#define PSWUSCFG0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                          0x00000002L
#define PSWUSCFG0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                               0x0000FE00L
#define PSWUSCFG0_PCIE_LINK_CNTL3__RESERVED_MASK                                                              0xFFFF0000L
//PSWUSCFG0_PCIE_LANE_ERROR_STATUS
#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                       0x0
#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                                     0x10
#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                         0x0000FFFFL
#define PSWUSCFG0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                                       0xFFFF0000L
//PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                             0x0
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                        0x4
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                               0x8
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                          0xc
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                               0x000FL
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                          0x0070L
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                 0x0F00L
#define PSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                            0x7000L
//PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
#define PSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
//PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
#define PSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
//PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
#define PSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
//PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
#define PSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
//PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
#define PSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
//PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                            0x0
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT                       0x4
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                              0x8
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                         0xc
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                              0x000FL
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                         0x0070L
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                                0x0F00L
#define PSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                           0x7000L
//PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
#define PSWUSCFG0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
//PSWUSCFG0_PCIE_ACS_CAP
#define PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                      0x0
#define PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                                   0x1
#define PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                                   0x2
#define PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                                0x3
#define PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                                    0x4
#define PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                                     0x5
#define PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                                  0x6
#define PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                             0x8
#define PSWUSCFG0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                        0x0001L
#define PSWUSCFG0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                                     0x0002L
#define PSWUSCFG0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                                     0x0004L
#define PSWUSCFG0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                                  0x0008L
#define PSWUSCFG0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                      0x0010L
#define PSWUSCFG0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                       0x0020L
#define PSWUSCFG0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                                    0x0040L
#define PSWUSCFG0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                               0xFF00L
//PSWUSCFG0_PCIE_ACS_CNTL
#define PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                                  0x0
#define PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                               0x1
#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                               0x2
#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                            0x3
#define PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                                0x4
#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                                 0x5
#define PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                              0x6
#define PSWUSCFG0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                                    0x0001L
#define PSWUSCFG0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                                 0x0002L
#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                                 0x0004L
#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                              0x0008L
#define PSWUSCFG0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                                  0x0010L
#define PSWUSCFG0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                                   0x0020L
#define PSWUSCFG0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                                0x0040L
//PSWUSCFG0_PCIE_MC_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                                         0x0
#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                                        0x10
#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                       0x14
#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                           0x0000FFFFL
#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                          0x000F0000L
#define PSWUSCFG0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                                         0xFFF00000L
//PSWUSCFG0_PCIE_MC_CAP
#define PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                            0x0
#define PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                                      0xf
#define PSWUSCFG0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                              0x003FL
#define PSWUSCFG0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                                        0x8000L
//PSWUSCFG0_PCIE_MC_CNTL
#define PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                           0x0
#define PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                              0xf
#define PSWUSCFG0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                             0x003FL
#define PSWUSCFG0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                                0x8000L
//PSWUSCFG0_PCIE_MC_ADDR0
#define PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                          0x0
#define PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                                        0xc
#define PSWUSCFG0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                            0x0000003FL
#define PSWUSCFG0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                          0xFFFFF000L
//PSWUSCFG0_PCIE_MC_ADDR1
#define PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                                        0x0
#define PSWUSCFG0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                          0xFFFFFFFFL
//PSWUSCFG0_PCIE_MC_RCV0
#define PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                           0x0
#define PSWUSCFG0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                             0xFFFFFFFFL
//PSWUSCFG0_PCIE_MC_RCV1
#define PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                           0x0
#define PSWUSCFG0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                             0xFFFFFFFFL
//PSWUSCFG0_PCIE_MC_BLOCK_ALL0
#define PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                                   0x0
#define PSWUSCFG0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                                     0xFFFFFFFFL
//PSWUSCFG0_PCIE_MC_BLOCK_ALL1
#define PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                                   0x0
#define PSWUSCFG0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                                     0xFFFFFFFFL
//PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0
#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                                0x0
#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                                  0xFFFFFFFFL
//PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1
#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                                0x0
#define PSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                                  0xFFFFFFFFL
//PCIE_MC_OVERLAY_BAR0
#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE__SHIFT                                                          0x0
#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0__SHIFT                                                         0x6
#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_SIZE_MASK                                                            0x0000003FL
#define PCIE_MC_OVERLAY_BAR0__MC_OVERLAY_BAR_0_MASK                                                           0xFFFFFFC0L
//PCIE_MC_OVERLAY_BAR1
#define PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1__SHIFT                                                         0x0
#define PCIE_MC_OVERLAY_BAR1__MC_OVERLAY_BAR_1_MASK                                                           0xFFFFFFFFL
//PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
#define PSWUSCFG0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
//PSWUSCFG0_PCIE_LTR_CAP
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                                0x0
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                                0xa
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                               0x10
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                               0x1a
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                                  0x000003FFL
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                                  0x00001C00L
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                                 0x03FF0000L
#define PSWUSCFG0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                                 0x1C000000L
//PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST
#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
#define PSWUSCFG0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
//PSWUSCFG0_PCIE_ARI_CAP
#define PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                               0x0
#define PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                                0x1
#define PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                                      0x8
#define PSWUSCFG0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                                 0x0001L
#define PSWUSCFG0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                                  0x0002L
#define PSWUSCFG0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                        0xFF00L
//PSWUSCFG0_PCIE_ARI_CNTL
#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                               0x0
#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                                0x1
#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                                    0x4
#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                                 0x0001L
#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                                  0x0002L
#define PSWUSCFG0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                                      0x0070L
//PCIE_L1_PM_SUB_CAP_LIST
#define PCIE_L1_PM_SUB_CAP_LIST__CAP_ID__SHIFT                                                                0x0
#define PCIE_L1_PM_SUB_CAP_LIST__CAP_VER__SHIFT                                                               0x10
#define PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR__SHIFT                                                              0x14
#define PCIE_L1_PM_SUB_CAP_LIST__CAP_ID_MASK                                                                  0x0000FFFFL
#define PCIE_L1_PM_SUB_CAP_LIST__CAP_VER_MASK                                                                 0x000F0000L
#define PCIE_L1_PM_SUB_CAP_LIST__NEXT_PTR_MASK                                                                0xFFF00000L
//PCIE_L1_PM_SUB_CAP
#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED__SHIFT                                                      0x0
#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED__SHIFT                                                      0x1
#define PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED__SHIFT                                                        0x2
#define PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED__SHIFT                                                        0x3
#define PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED__SHIFT                                                        0x4
#define PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME__SHIFT                                                       0x8
#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE__SHIFT                                                      0x10
#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE__SHIFT                                                      0x13
#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_2_SUPPORTED_MASK                                                        0x00000001L
#define PCIE_L1_PM_SUB_CAP__PCI_PM_L1_1_SUPPORTED_MASK                                                        0x00000002L
#define PCIE_L1_PM_SUB_CAP__ASPM_L1_2_SUPPORTED_MASK                                                          0x00000004L
#define PCIE_L1_PM_SUB_CAP__ASPM_L1_1_SUPPORTED_MASK                                                          0x00000008L
#define PCIE_L1_PM_SUB_CAP__L1_PM_SUB_SUPPORTED_MASK                                                          0x00000010L
#define PCIE_L1_PM_SUB_CAP__PORT_CM_RESTORE_TIME_MASK                                                         0x0000FF00L
#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_SCALE_MASK                                                        0x00030000L
#define PCIE_L1_PM_SUB_CAP__PORT_T_POWER_ON_VALUE_MASK                                                        0x00F80000L
//PCIE_L1_PM_SUB_CNTL
#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN__SHIFT                                                            0x0
#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN__SHIFT                                                            0x1
#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN__SHIFT                                                              0x2
#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN__SHIFT                                                              0x3
#define PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME__SHIFT                                                  0x8
#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE__SHIFT                                                  0x10
#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE__SHIFT                                                  0x1d
#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_2_EN_MASK                                                              0x00000001L
#define PCIE_L1_PM_SUB_CNTL__PCI_PM_L1_1_EN_MASK                                                              0x00000002L
#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_2_EN_MASK                                                                0x00000004L
#define PCIE_L1_PM_SUB_CNTL__ASPM_L1_1_EN_MASK                                                                0x00000008L
#define PCIE_L1_PM_SUB_CNTL__COMMON_MODE_RESTORE_TIME_MASK                                                    0x0000FF00L
#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_VALUE_MASK                                                    0x03FF0000L
#define PCIE_L1_PM_SUB_CNTL__LTR_L1_2_THRESHOLD_SCALE_MASK                                                    0xE0000000L
//PCIE_L1_PM_SUB_CNTL2
#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE__SHIFT                                                         0x0
#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE__SHIFT                                                         0x3
#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_SCALE_MASK                                                           0x00000003L
#define PCIE_L1_PM_SUB_CNTL2__T_POWER_ON_VALUE_MASK                                                           0x000000F8L
//PCIE_ESM_CAP_LIST
#define PCIE_ESM_CAP_LIST__CAP_ID__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_LIST__CAP_VER__SHIFT                                                                     0x10
#define PCIE_ESM_CAP_LIST__NEXT_PTR__SHIFT                                                                    0x14
#define PCIE_ESM_CAP_LIST__CAP_ID_MASK                                                                        0x0000FFFFL
#define PCIE_ESM_CAP_LIST__CAP_VER_MASK                                                                       0x000F0000L
#define PCIE_ESM_CAP_LIST__NEXT_PTR_MASK                                                                      0xFFF00000L
//PCIE_ESM_HEADER_1
#define PCIE_ESM_HEADER_1__ESM_VENDOR_ID__SHIFT                                                               0x0
#define PCIE_ESM_HEADER_1__ESM_CAP_REV__SHIFT                                                                 0x10
#define PCIE_ESM_HEADER_1__ESM_CAP_LEN__SHIFT                                                                 0x14
#define PCIE_ESM_HEADER_1__ESM_VENDOR_ID_MASK                                                                 0x0000FFFFL
#define PCIE_ESM_HEADER_1__ESM_CAP_REV_MASK                                                                   0x000F0000L
#define PCIE_ESM_HEADER_1__ESM_CAP_LEN_MASK                                                                   0xFFF00000L
//PCIE_ESM_HEADER_2
#define PCIE_ESM_HEADER_2__CAP_ID__SHIFT                                                                      0x0
#define PCIE_ESM_HEADER_2__CAP_ID_MASK                                                                        0xFFFFL
//PCIE_ESM_STATUS
#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL__SHIFT                                                            0x0
#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE__SHIFT                                                          0x9
#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_VAL_MASK                                                              0x01FFL
#define PCIE_ESM_STATUS__MIN_TIME_IN_EI_SCALE_MASK                                                            0x0E00L
//PCIE_ESM_CTRL
#define PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE__SHIFT                                                             0x0
#define PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE__SHIFT                                                             0x8
#define PCIE_ESM_CTRL__ESM_ENABLED__SHIFT                                                                     0xf
#define PCIE_ESM_CTRL__ESM_GEN_3_DATA_RATE_MASK                                                               0x007FL
#define PCIE_ESM_CTRL__ESM_GEN_4_DATA_RATE_MASK                                                               0x7F00L
#define PCIE_ESM_CTRL__ESM_ENABLED_MASK                                                                       0x8000L
//PCIE_ESM_CAP_1
#define PCIE_ESM_CAP_1__ESM_8P0G__SHIFT                                                                       0x0
#define PCIE_ESM_CAP_1__ESM_8P1G__SHIFT                                                                       0x1
#define PCIE_ESM_CAP_1__ESM_8P2G__SHIFT                                                                       0x2
#define PCIE_ESM_CAP_1__ESM_8P3G__SHIFT                                                                       0x3
#define PCIE_ESM_CAP_1__ESM_8P4G__SHIFT                                                                       0x4
#define PCIE_ESM_CAP_1__ESM_8P5G__SHIFT                                                                       0x5
#define PCIE_ESM_CAP_1__ESM_8P6G__SHIFT                                                                       0x6
#define PCIE_ESM_CAP_1__ESM_8P7G__SHIFT                                                                       0x7
#define PCIE_ESM_CAP_1__ESM_8P8G__SHIFT                                                                       0x8
#define PCIE_ESM_CAP_1__ESM_8P9G__SHIFT                                                                       0x9
#define PCIE_ESM_CAP_1__ESM_9P0G__SHIFT                                                                       0xa
#define PCIE_ESM_CAP_1__ESM_9P1G__SHIFT                                                                       0xb
#define PCIE_ESM_CAP_1__ESM_9P2G__SHIFT                                                                       0xc
#define PCIE_ESM_CAP_1__ESM_9P3G__SHIFT                                                                       0xd
#define PCIE_ESM_CAP_1__ESM_9P4G__SHIFT                                                                       0xe
#define PCIE_ESM_CAP_1__ESM_9P5G__SHIFT                                                                       0xf
#define PCIE_ESM_CAP_1__ESM_9P6G__SHIFT                                                                       0x10
#define PCIE_ESM_CAP_1__ESM_9P7G__SHIFT                                                                       0x11
#define PCIE_ESM_CAP_1__ESM_9P8G__SHIFT                                                                       0x12
#define PCIE_ESM_CAP_1__ESM_9P9G__SHIFT                                                                       0x13
#define PCIE_ESM_CAP_1__ESM_10P0G__SHIFT                                                                      0x14
#define PCIE_ESM_CAP_1__ESM_10P1G__SHIFT                                                                      0x15
#define PCIE_ESM_CAP_1__ESM_10P2G__SHIFT                                                                      0x16
#define PCIE_ESM_CAP_1__ESM_10P3G__SHIFT                                                                      0x17
#define PCIE_ESM_CAP_1__ESM_10P4G__SHIFT                                                                      0x18
#define PCIE_ESM_CAP_1__ESM_10P5G__SHIFT                                                                      0x19
#define PCIE_ESM_CAP_1__ESM_10P6G__SHIFT                                                                      0x1a
#define PCIE_ESM_CAP_1__ESM_10P7G__SHIFT                                                                      0x1b
#define PCIE_ESM_CAP_1__ESM_10P8G__SHIFT                                                                      0x1c
#define PCIE_ESM_CAP_1__ESM_10P9G__SHIFT                                                                      0x1d
#define PCIE_ESM_CAP_1__ESM_8P0G_MASK                                                                         0x00000001L
#define PCIE_ESM_CAP_1__ESM_8P1G_MASK                                                                         0x00000002L
#define PCIE_ESM_CAP_1__ESM_8P2G_MASK                                                                         0x00000004L
#define PCIE_ESM_CAP_1__ESM_8P3G_MASK                                                                         0x00000008L
#define PCIE_ESM_CAP_1__ESM_8P4G_MASK                                                                         0x00000010L
#define PCIE_ESM_CAP_1__ESM_8P5G_MASK                                                                         0x00000020L
#define PCIE_ESM_CAP_1__ESM_8P6G_MASK                                                                         0x00000040L
#define PCIE_ESM_CAP_1__ESM_8P7G_MASK                                                                         0x00000080L
#define PCIE_ESM_CAP_1__ESM_8P8G_MASK                                                                         0x00000100L
#define PCIE_ESM_CAP_1__ESM_8P9G_MASK                                                                         0x00000200L
#define PCIE_ESM_CAP_1__ESM_9P0G_MASK                                                                         0x00000400L
#define PCIE_ESM_CAP_1__ESM_9P1G_MASK                                                                         0x00000800L
#define PCIE_ESM_CAP_1__ESM_9P2G_MASK                                                                         0x00001000L
#define PCIE_ESM_CAP_1__ESM_9P3G_MASK                                                                         0x00002000L
#define PCIE_ESM_CAP_1__ESM_9P4G_MASK                                                                         0x00004000L
#define PCIE_ESM_CAP_1__ESM_9P5G_MASK                                                                         0x00008000L
#define PCIE_ESM_CAP_1__ESM_9P6G_MASK                                                                         0x00010000L
#define PCIE_ESM_CAP_1__ESM_9P7G_MASK                                                                         0x00020000L
#define PCIE_ESM_CAP_1__ESM_9P8G_MASK                                                                         0x00040000L
#define PCIE_ESM_CAP_1__ESM_9P9G_MASK                                                                         0x00080000L
#define PCIE_ESM_CAP_1__ESM_10P0G_MASK                                                                        0x00100000L
#define PCIE_ESM_CAP_1__ESM_10P1G_MASK                                                                        0x00200000L
#define PCIE_ESM_CAP_1__ESM_10P2G_MASK                                                                        0x00400000L
#define PCIE_ESM_CAP_1__ESM_10P3G_MASK                                                                        0x00800000L
#define PCIE_ESM_CAP_1__ESM_10P4G_MASK                                                                        0x01000000L
#define PCIE_ESM_CAP_1__ESM_10P5G_MASK                                                                        0x02000000L
#define PCIE_ESM_CAP_1__ESM_10P6G_MASK                                                                        0x04000000L
#define PCIE_ESM_CAP_1__ESM_10P7G_MASK                                                                        0x08000000L
#define PCIE_ESM_CAP_1__ESM_10P8G_MASK                                                                        0x10000000L
#define PCIE_ESM_CAP_1__ESM_10P9G_MASK                                                                        0x20000000L
//PCIE_ESM_CAP_2
#define PCIE_ESM_CAP_2__ESM_11P0G__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_2__ESM_11P1G__SHIFT                                                                      0x1
#define PCIE_ESM_CAP_2__ESM_11P2G__SHIFT                                                                      0x2
#define PCIE_ESM_CAP_2__ESM_11P3G__SHIFT                                                                      0x3
#define PCIE_ESM_CAP_2__ESM_11P4G__SHIFT                                                                      0x4
#define PCIE_ESM_CAP_2__ESM_11P5G__SHIFT                                                                      0x5
#define PCIE_ESM_CAP_2__ESM_11P6G__SHIFT                                                                      0x6
#define PCIE_ESM_CAP_2__ESM_11P7G__SHIFT                                                                      0x7
#define PCIE_ESM_CAP_2__ESM_11P8G__SHIFT                                                                      0x8
#define PCIE_ESM_CAP_2__ESM_11P9G__SHIFT                                                                      0x9
#define PCIE_ESM_CAP_2__ESM_12P0G__SHIFT                                                                      0xa
#define PCIE_ESM_CAP_2__ESM_12P1G__SHIFT                                                                      0xb
#define PCIE_ESM_CAP_2__ESM_12P2G__SHIFT                                                                      0xc
#define PCIE_ESM_CAP_2__ESM_12P3G__SHIFT                                                                      0xd
#define PCIE_ESM_CAP_2__ESM_12P4G__SHIFT                                                                      0xe
#define PCIE_ESM_CAP_2__ESM_12P5G__SHIFT                                                                      0xf
#define PCIE_ESM_CAP_2__ESM_12P6G__SHIFT                                                                      0x10
#define PCIE_ESM_CAP_2__ESM_12P7G__SHIFT                                                                      0x11
#define PCIE_ESM_CAP_2__ESM_12P8G__SHIFT                                                                      0x12
#define PCIE_ESM_CAP_2__ESM_12P9G__SHIFT                                                                      0x13
#define PCIE_ESM_CAP_2__ESM_13P0G__SHIFT                                                                      0x14
#define PCIE_ESM_CAP_2__ESM_13P1G__SHIFT                                                                      0x15
#define PCIE_ESM_CAP_2__ESM_13P2G__SHIFT                                                                      0x16
#define PCIE_ESM_CAP_2__ESM_13P3G__SHIFT                                                                      0x17
#define PCIE_ESM_CAP_2__ESM_13P4G__SHIFT                                                                      0x18
#define PCIE_ESM_CAP_2__ESM_13P5G__SHIFT                                                                      0x19
#define PCIE_ESM_CAP_2__ESM_13P6G__SHIFT                                                                      0x1a
#define PCIE_ESM_CAP_2__ESM_13P7G__SHIFT                                                                      0x1b
#define PCIE_ESM_CAP_2__ESM_13P8G__SHIFT                                                                      0x1c
#define PCIE_ESM_CAP_2__ESM_13P9G__SHIFT                                                                      0x1d
#define PCIE_ESM_CAP_2__ESM_11P0G_MASK                                                                        0x00000001L
#define PCIE_ESM_CAP_2__ESM_11P1G_MASK                                                                        0x00000002L
#define PCIE_ESM_CAP_2__ESM_11P2G_MASK                                                                        0x00000004L
#define PCIE_ESM_CAP_2__ESM_11P3G_MASK                                                                        0x00000008L
#define PCIE_ESM_CAP_2__ESM_11P4G_MASK                                                                        0x00000010L
#define PCIE_ESM_CAP_2__ESM_11P5G_MASK                                                                        0x00000020L
#define PCIE_ESM_CAP_2__ESM_11P6G_MASK                                                                        0x00000040L
#define PCIE_ESM_CAP_2__ESM_11P7G_MASK                                                                        0x00000080L
#define PCIE_ESM_CAP_2__ESM_11P8G_MASK                                                                        0x00000100L
#define PCIE_ESM_CAP_2__ESM_11P9G_MASK                                                                        0x00000200L
#define PCIE_ESM_CAP_2__ESM_12P0G_MASK                                                                        0x00000400L
#define PCIE_ESM_CAP_2__ESM_12P1G_MASK                                                                        0x00000800L
#define PCIE_ESM_CAP_2__ESM_12P2G_MASK                                                                        0x00001000L
#define PCIE_ESM_CAP_2__ESM_12P3G_MASK                                                                        0x00002000L
#define PCIE_ESM_CAP_2__ESM_12P4G_MASK                                                                        0x00004000L
#define PCIE_ESM_CAP_2__ESM_12P5G_MASK                                                                        0x00008000L
#define PCIE_ESM_CAP_2__ESM_12P6G_MASK                                                                        0x00010000L
#define PCIE_ESM_CAP_2__ESM_12P7G_MASK                                                                        0x00020000L
#define PCIE_ESM_CAP_2__ESM_12P8G_MASK                                                                        0x00040000L
#define PCIE_ESM_CAP_2__ESM_12P9G_MASK                                                                        0x00080000L
#define PCIE_ESM_CAP_2__ESM_13P0G_MASK                                                                        0x00100000L
#define PCIE_ESM_CAP_2__ESM_13P1G_MASK                                                                        0x00200000L
#define PCIE_ESM_CAP_2__ESM_13P2G_MASK                                                                        0x00400000L
#define PCIE_ESM_CAP_2__ESM_13P3G_MASK                                                                        0x00800000L
#define PCIE_ESM_CAP_2__ESM_13P4G_MASK                                                                        0x01000000L
#define PCIE_ESM_CAP_2__ESM_13P5G_MASK                                                                        0x02000000L
#define PCIE_ESM_CAP_2__ESM_13P6G_MASK                                                                        0x04000000L
#define PCIE_ESM_CAP_2__ESM_13P7G_MASK                                                                        0x08000000L
#define PCIE_ESM_CAP_2__ESM_13P8G_MASK                                                                        0x10000000L
#define PCIE_ESM_CAP_2__ESM_13P9G_MASK                                                                        0x20000000L
//PCIE_ESM_CAP_3
#define PCIE_ESM_CAP_3__ESM_14P0G__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_3__ESM_14P1G__SHIFT                                                                      0x1
#define PCIE_ESM_CAP_3__ESM_14P2G__SHIFT                                                                      0x2
#define PCIE_ESM_CAP_3__ESM_14P3G__SHIFT                                                                      0x3
#define PCIE_ESM_CAP_3__ESM_14P4G__SHIFT                                                                      0x4
#define PCIE_ESM_CAP_3__ESM_14P5G__SHIFT                                                                      0x5
#define PCIE_ESM_CAP_3__ESM_14P6G__SHIFT                                                                      0x6
#define PCIE_ESM_CAP_3__ESM_14P7G__SHIFT                                                                      0x7
#define PCIE_ESM_CAP_3__ESM_14P8G__SHIFT                                                                      0x8
#define PCIE_ESM_CAP_3__ESM_14P9G__SHIFT                                                                      0x9
#define PCIE_ESM_CAP_3__ESM_15P0G__SHIFT                                                                      0xa
#define PCIE_ESM_CAP_3__ESM_15P1G__SHIFT                                                                      0xb
#define PCIE_ESM_CAP_3__ESM_15P2G__SHIFT                                                                      0xc
#define PCIE_ESM_CAP_3__ESM_15P3G__SHIFT                                                                      0xd
#define PCIE_ESM_CAP_3__ESM_15P4G__SHIFT                                                                      0xe
#define PCIE_ESM_CAP_3__ESM_15P5G__SHIFT                                                                      0xf
#define PCIE_ESM_CAP_3__ESM_15P6G__SHIFT                                                                      0x10
#define PCIE_ESM_CAP_3__ESM_15P7G__SHIFT                                                                      0x11
#define PCIE_ESM_CAP_3__ESM_15P8G__SHIFT                                                                      0x12
#define PCIE_ESM_CAP_3__ESM_15P9G__SHIFT                                                                      0x13
#define PCIE_ESM_CAP_3__ESM_14P0G_MASK                                                                        0x00000001L
#define PCIE_ESM_CAP_3__ESM_14P1G_MASK                                                                        0x00000002L
#define PCIE_ESM_CAP_3__ESM_14P2G_MASK                                                                        0x00000004L
#define PCIE_ESM_CAP_3__ESM_14P3G_MASK                                                                        0x00000008L
#define PCIE_ESM_CAP_3__ESM_14P4G_MASK                                                                        0x00000010L
#define PCIE_ESM_CAP_3__ESM_14P5G_MASK                                                                        0x00000020L
#define PCIE_ESM_CAP_3__ESM_14P6G_MASK                                                                        0x00000040L
#define PCIE_ESM_CAP_3__ESM_14P7G_MASK                                                                        0x00000080L
#define PCIE_ESM_CAP_3__ESM_14P8G_MASK                                                                        0x00000100L
#define PCIE_ESM_CAP_3__ESM_14P9G_MASK                                                                        0x00000200L
#define PCIE_ESM_CAP_3__ESM_15P0G_MASK                                                                        0x00000400L
#define PCIE_ESM_CAP_3__ESM_15P1G_MASK                                                                        0x00000800L
#define PCIE_ESM_CAP_3__ESM_15P2G_MASK                                                                        0x00001000L
#define PCIE_ESM_CAP_3__ESM_15P3G_MASK                                                                        0x00002000L
#define PCIE_ESM_CAP_3__ESM_15P4G_MASK                                                                        0x00004000L
#define PCIE_ESM_CAP_3__ESM_15P5G_MASK                                                                        0x00008000L
#define PCIE_ESM_CAP_3__ESM_15P6G_MASK                                                                        0x00010000L
#define PCIE_ESM_CAP_3__ESM_15P7G_MASK                                                                        0x00020000L
#define PCIE_ESM_CAP_3__ESM_15P8G_MASK                                                                        0x00040000L
#define PCIE_ESM_CAP_3__ESM_15P9G_MASK                                                                        0x00080000L
//PCIE_ESM_CAP_4
#define PCIE_ESM_CAP_4__ESM_16P0G__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_4__ESM_16P1G__SHIFT                                                                      0x1
#define PCIE_ESM_CAP_4__ESM_16P2G__SHIFT                                                                      0x2
#define PCIE_ESM_CAP_4__ESM_16P3G__SHIFT                                                                      0x3
#define PCIE_ESM_CAP_4__ESM_16P4G__SHIFT                                                                      0x4
#define PCIE_ESM_CAP_4__ESM_16P5G__SHIFT                                                                      0x5
#define PCIE_ESM_CAP_4__ESM_16P6G__SHIFT                                                                      0x6
#define PCIE_ESM_CAP_4__ESM_16P7G__SHIFT                                                                      0x7
#define PCIE_ESM_CAP_4__ESM_16P8G__SHIFT                                                                      0x8
#define PCIE_ESM_CAP_4__ESM_16P9G__SHIFT                                                                      0x9
#define PCIE_ESM_CAP_4__ESM_17P0G__SHIFT                                                                      0xa
#define PCIE_ESM_CAP_4__ESM_17P1G__SHIFT                                                                      0xb
#define PCIE_ESM_CAP_4__ESM_17P2G__SHIFT                                                                      0xc
#define PCIE_ESM_CAP_4__ESM_17P3G__SHIFT                                                                      0xd
#define PCIE_ESM_CAP_4__ESM_17P4G__SHIFT                                                                      0xe
#define PCIE_ESM_CAP_4__ESM_17P5G__SHIFT                                                                      0xf
#define PCIE_ESM_CAP_4__ESM_17P6G__SHIFT                                                                      0x10
#define PCIE_ESM_CAP_4__ESM_17P7G__SHIFT                                                                      0x11
#define PCIE_ESM_CAP_4__ESM_17P8G__SHIFT                                                                      0x12
#define PCIE_ESM_CAP_4__ESM_17P9G__SHIFT                                                                      0x13
#define PCIE_ESM_CAP_4__ESM_18P0G__SHIFT                                                                      0x14
#define PCIE_ESM_CAP_4__ESM_18P1G__SHIFT                                                                      0x15
#define PCIE_ESM_CAP_4__ESM_18P2G__SHIFT                                                                      0x16
#define PCIE_ESM_CAP_4__ESM_18P3G__SHIFT                                                                      0x17
#define PCIE_ESM_CAP_4__ESM_18P4G__SHIFT                                                                      0x18
#define PCIE_ESM_CAP_4__ESM_18P5G__SHIFT                                                                      0x19
#define PCIE_ESM_CAP_4__ESM_18P6G__SHIFT                                                                      0x1a
#define PCIE_ESM_CAP_4__ESM_18P7G__SHIFT                                                                      0x1b
#define PCIE_ESM_CAP_4__ESM_18P8G__SHIFT                                                                      0x1c
#define PCIE_ESM_CAP_4__ESM_18P9G__SHIFT                                                                      0x1d
#define PCIE_ESM_CAP_4__ESM_16P0G_MASK                                                                        0x00000001L
#define PCIE_ESM_CAP_4__ESM_16P1G_MASK                                                                        0x00000002L
#define PCIE_ESM_CAP_4__ESM_16P2G_MASK                                                                        0x00000004L
#define PCIE_ESM_CAP_4__ESM_16P3G_MASK                                                                        0x00000008L
#define PCIE_ESM_CAP_4__ESM_16P4G_MASK                                                                        0x00000010L
#define PCIE_ESM_CAP_4__ESM_16P5G_MASK                                                                        0x00000020L
#define PCIE_ESM_CAP_4__ESM_16P6G_MASK                                                                        0x00000040L
#define PCIE_ESM_CAP_4__ESM_16P7G_MASK                                                                        0x00000080L
#define PCIE_ESM_CAP_4__ESM_16P8G_MASK                                                                        0x00000100L
#define PCIE_ESM_CAP_4__ESM_16P9G_MASK                                                                        0x00000200L
#define PCIE_ESM_CAP_4__ESM_17P0G_MASK                                                                        0x00000400L
#define PCIE_ESM_CAP_4__ESM_17P1G_MASK                                                                        0x00000800L
#define PCIE_ESM_CAP_4__ESM_17P2G_MASK                                                                        0x00001000L
#define PCIE_ESM_CAP_4__ESM_17P3G_MASK                                                                        0x00002000L
#define PCIE_ESM_CAP_4__ESM_17P4G_MASK                                                                        0x00004000L
#define PCIE_ESM_CAP_4__ESM_17P5G_MASK                                                                        0x00008000L
#define PCIE_ESM_CAP_4__ESM_17P6G_MASK                                                                        0x00010000L
#define PCIE_ESM_CAP_4__ESM_17P7G_MASK                                                                        0x00020000L
#define PCIE_ESM_CAP_4__ESM_17P8G_MASK                                                                        0x00040000L
#define PCIE_ESM_CAP_4__ESM_17P9G_MASK                                                                        0x00080000L
#define PCIE_ESM_CAP_4__ESM_18P0G_MASK                                                                        0x00100000L
#define PCIE_ESM_CAP_4__ESM_18P1G_MASK                                                                        0x00200000L
#define PCIE_ESM_CAP_4__ESM_18P2G_MASK                                                                        0x00400000L
#define PCIE_ESM_CAP_4__ESM_18P3G_MASK                                                                        0x00800000L
#define PCIE_ESM_CAP_4__ESM_18P4G_MASK                                                                        0x01000000L
#define PCIE_ESM_CAP_4__ESM_18P5G_MASK                                                                        0x02000000L
#define PCIE_ESM_CAP_4__ESM_18P6G_MASK                                                                        0x04000000L
#define PCIE_ESM_CAP_4__ESM_18P7G_MASK                                                                        0x08000000L
#define PCIE_ESM_CAP_4__ESM_18P8G_MASK                                                                        0x10000000L
#define PCIE_ESM_CAP_4__ESM_18P9G_MASK                                                                        0x20000000L
//PCIE_ESM_CAP_5
#define PCIE_ESM_CAP_5__ESM_19P0G__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_5__ESM_19P1G__SHIFT                                                                      0x1
#define PCIE_ESM_CAP_5__ESM_19P2G__SHIFT                                                                      0x2
#define PCIE_ESM_CAP_5__ESM_19P3G__SHIFT                                                                      0x3
#define PCIE_ESM_CAP_5__ESM_19P4G__SHIFT                                                                      0x4
#define PCIE_ESM_CAP_5__ESM_19P5G__SHIFT                                                                      0x5
#define PCIE_ESM_CAP_5__ESM_19P6G__SHIFT                                                                      0x6
#define PCIE_ESM_CAP_5__ESM_19P7G__SHIFT                                                                      0x7
#define PCIE_ESM_CAP_5__ESM_19P8G__SHIFT                                                                      0x8
#define PCIE_ESM_CAP_5__ESM_19P9G__SHIFT                                                                      0x9
#define PCIE_ESM_CAP_5__ESM_20P0G__SHIFT                                                                      0xa
#define PCIE_ESM_CAP_5__ESM_20P1G__SHIFT                                                                      0xb
#define PCIE_ESM_CAP_5__ESM_20P2G__SHIFT                                                                      0xc
#define PCIE_ESM_CAP_5__ESM_20P3G__SHIFT                                                                      0xd
#define PCIE_ESM_CAP_5__ESM_20P4G__SHIFT                                                                      0xe
#define PCIE_ESM_CAP_5__ESM_20P5G__SHIFT                                                                      0xf
#define PCIE_ESM_CAP_5__ESM_20P6G__SHIFT                                                                      0x10
#define PCIE_ESM_CAP_5__ESM_20P7G__SHIFT                                                                      0x11
#define PCIE_ESM_CAP_5__ESM_20P8G__SHIFT                                                                      0x12
#define PCIE_ESM_CAP_5__ESM_20P9G__SHIFT                                                                      0x13
#define PCIE_ESM_CAP_5__ESM_21P0G__SHIFT                                                                      0x14
#define PCIE_ESM_CAP_5__ESM_21P1G__SHIFT                                                                      0x15
#define PCIE_ESM_CAP_5__ESM_21P2G__SHIFT                                                                      0x16
#define PCIE_ESM_CAP_5__ESM_21P3G__SHIFT                                                                      0x17
#define PCIE_ESM_CAP_5__ESM_21P4G__SHIFT                                                                      0x18
#define PCIE_ESM_CAP_5__ESM_21P5G__SHIFT                                                                      0x19
#define PCIE_ESM_CAP_5__ESM_21P6G__SHIFT                                                                      0x1a
#define PCIE_ESM_CAP_5__ESM_21P7G__SHIFT                                                                      0x1b
#define PCIE_ESM_CAP_5__ESM_21P8G__SHIFT                                                                      0x1c
#define PCIE_ESM_CAP_5__ESM_21P9G__SHIFT                                                                      0x1d
#define PCIE_ESM_CAP_5__ESM_19P0G_MASK                                                                        0x00000001L
#define PCIE_ESM_CAP_5__ESM_19P1G_MASK                                                                        0x00000002L
#define PCIE_ESM_CAP_5__ESM_19P2G_MASK                                                                        0x00000004L
#define PCIE_ESM_CAP_5__ESM_19P3G_MASK                                                                        0x00000008L
#define PCIE_ESM_CAP_5__ESM_19P4G_MASK                                                                        0x00000010L
#define PCIE_ESM_CAP_5__ESM_19P5G_MASK                                                                        0x00000020L
#define PCIE_ESM_CAP_5__ESM_19P6G_MASK                                                                        0x00000040L
#define PCIE_ESM_CAP_5__ESM_19P7G_MASK                                                                        0x00000080L
#define PCIE_ESM_CAP_5__ESM_19P8G_MASK                                                                        0x00000100L
#define PCIE_ESM_CAP_5__ESM_19P9G_MASK                                                                        0x00000200L
#define PCIE_ESM_CAP_5__ESM_20P0G_MASK                                                                        0x00000400L
#define PCIE_ESM_CAP_5__ESM_20P1G_MASK                                                                        0x00000800L
#define PCIE_ESM_CAP_5__ESM_20P2G_MASK                                                                        0x00001000L
#define PCIE_ESM_CAP_5__ESM_20P3G_MASK                                                                        0x00002000L
#define PCIE_ESM_CAP_5__ESM_20P4G_MASK                                                                        0x00004000L
#define PCIE_ESM_CAP_5__ESM_20P5G_MASK                                                                        0x00008000L
#define PCIE_ESM_CAP_5__ESM_20P6G_MASK                                                                        0x00010000L
#define PCIE_ESM_CAP_5__ESM_20P7G_MASK                                                                        0x00020000L
#define PCIE_ESM_CAP_5__ESM_20P8G_MASK                                                                        0x00040000L
#define PCIE_ESM_CAP_5__ESM_20P9G_MASK                                                                        0x00080000L
#define PCIE_ESM_CAP_5__ESM_21P0G_MASK                                                                        0x00100000L
#define PCIE_ESM_CAP_5__ESM_21P1G_MASK                                                                        0x00200000L
#define PCIE_ESM_CAP_5__ESM_21P2G_MASK                                                                        0x00400000L
#define PCIE_ESM_CAP_5__ESM_21P3G_MASK                                                                        0x00800000L
#define PCIE_ESM_CAP_5__ESM_21P4G_MASK                                                                        0x01000000L
#define PCIE_ESM_CAP_5__ESM_21P5G_MASK                                                                        0x02000000L
#define PCIE_ESM_CAP_5__ESM_21P6G_MASK                                                                        0x04000000L
#define PCIE_ESM_CAP_5__ESM_21P7G_MASK                                                                        0x08000000L
#define PCIE_ESM_CAP_5__ESM_21P8G_MASK                                                                        0x10000000L
#define PCIE_ESM_CAP_5__ESM_21P9G_MASK                                                                        0x20000000L
//PCIE_ESM_CAP_6
#define PCIE_ESM_CAP_6__ESM_22P0G__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_6__ESM_22P1G__SHIFT                                                                      0x1
#define PCIE_ESM_CAP_6__ESM_22P2G__SHIFT                                                                      0x2
#define PCIE_ESM_CAP_6__ESM_22P3G__SHIFT                                                                      0x3
#define PCIE_ESM_CAP_6__ESM_22P4G__SHIFT                                                                      0x4
#define PCIE_ESM_CAP_6__ESM_22P5G__SHIFT                                                                      0x5
#define PCIE_ESM_CAP_6__ESM_22P6G__SHIFT                                                                      0x6
#define PCIE_ESM_CAP_6__ESM_22P7G__SHIFT                                                                      0x7
#define PCIE_ESM_CAP_6__ESM_22P8G__SHIFT                                                                      0x8
#define PCIE_ESM_CAP_6__ESM_22P9G__SHIFT                                                                      0x9
#define PCIE_ESM_CAP_6__ESM_23P0G__SHIFT                                                                      0xa
#define PCIE_ESM_CAP_6__ESM_23P1G__SHIFT                                                                      0xb
#define PCIE_ESM_CAP_6__ESM_23P2G__SHIFT                                                                      0xc
#define PCIE_ESM_CAP_6__ESM_23P3G__SHIFT                                                                      0xd
#define PCIE_ESM_CAP_6__ESM_23P4G__SHIFT                                                                      0xe
#define PCIE_ESM_CAP_6__ESM_23P5G__SHIFT                                                                      0xf
#define PCIE_ESM_CAP_6__ESM_23P6G__SHIFT                                                                      0x10
#define PCIE_ESM_CAP_6__ESM_23P7G__SHIFT                                                                      0x11
#define PCIE_ESM_CAP_6__ESM_23P8G__SHIFT                                                                      0x12
#define PCIE_ESM_CAP_6__ESM_23P9G__SHIFT                                                                      0x13
#define PCIE_ESM_CAP_6__ESM_24P0G__SHIFT                                                                      0x14
#define PCIE_ESM_CAP_6__ESM_24P1G__SHIFT                                                                      0x15
#define PCIE_ESM_CAP_6__ESM_24P2G__SHIFT                                                                      0x16
#define PCIE_ESM_CAP_6__ESM_24P3G__SHIFT                                                                      0x17
#define PCIE_ESM_CAP_6__ESM_24P4G__SHIFT                                                                      0x18
#define PCIE_ESM_CAP_6__ESM_24P5G__SHIFT                                                                      0x19
#define PCIE_ESM_CAP_6__ESM_24P6G__SHIFT                                                                      0x1a
#define PCIE_ESM_CAP_6__ESM_24P7G__SHIFT                                                                      0x1b
#define PCIE_ESM_CAP_6__ESM_24P8G__SHIFT                                                                      0x1c
#define PCIE_ESM_CAP_6__ESM_24P9G__SHIFT                                                                      0x1d
#define PCIE_ESM_CAP_6__ESM_22P0G_MASK                                                                        0x00000001L
#define PCIE_ESM_CAP_6__ESM_22P1G_MASK                                                                        0x00000002L
#define PCIE_ESM_CAP_6__ESM_22P2G_MASK                                                                        0x00000004L
#define PCIE_ESM_CAP_6__ESM_22P3G_MASK                                                                        0x00000008L
#define PCIE_ESM_CAP_6__ESM_22P4G_MASK                                                                        0x00000010L
#define PCIE_ESM_CAP_6__ESM_22P5G_MASK                                                                        0x00000020L
#define PCIE_ESM_CAP_6__ESM_22P6G_MASK                                                                        0x00000040L
#define PCIE_ESM_CAP_6__ESM_22P7G_MASK                                                                        0x00000080L
#define PCIE_ESM_CAP_6__ESM_22P8G_MASK                                                                        0x00000100L
#define PCIE_ESM_CAP_6__ESM_22P9G_MASK                                                                        0x00000200L
#define PCIE_ESM_CAP_6__ESM_23P0G_MASK                                                                        0x00000400L
#define PCIE_ESM_CAP_6__ESM_23P1G_MASK                                                                        0x00000800L
#define PCIE_ESM_CAP_6__ESM_23P2G_MASK                                                                        0x00001000L
#define PCIE_ESM_CAP_6__ESM_23P3G_MASK                                                                        0x00002000L
#define PCIE_ESM_CAP_6__ESM_23P4G_MASK                                                                        0x00004000L
#define PCIE_ESM_CAP_6__ESM_23P5G_MASK                                                                        0x00008000L
#define PCIE_ESM_CAP_6__ESM_23P6G_MASK                                                                        0x00010000L
#define PCIE_ESM_CAP_6__ESM_23P7G_MASK                                                                        0x00020000L
#define PCIE_ESM_CAP_6__ESM_23P8G_MASK                                                                        0x00040000L
#define PCIE_ESM_CAP_6__ESM_23P9G_MASK                                                                        0x00080000L
#define PCIE_ESM_CAP_6__ESM_24P0G_MASK                                                                        0x00100000L
#define PCIE_ESM_CAP_6__ESM_24P1G_MASK                                                                        0x00200000L
#define PCIE_ESM_CAP_6__ESM_24P2G_MASK                                                                        0x00400000L
#define PCIE_ESM_CAP_6__ESM_24P3G_MASK                                                                        0x00800000L
#define PCIE_ESM_CAP_6__ESM_24P4G_MASK                                                                        0x01000000L
#define PCIE_ESM_CAP_6__ESM_24P5G_MASK                                                                        0x02000000L
#define PCIE_ESM_CAP_6__ESM_24P6G_MASK                                                                        0x04000000L
#define PCIE_ESM_CAP_6__ESM_24P7G_MASK                                                                        0x08000000L
#define PCIE_ESM_CAP_6__ESM_24P8G_MASK                                                                        0x10000000L
#define PCIE_ESM_CAP_6__ESM_24P9G_MASK                                                                        0x20000000L
//PCIE_ESM_CAP_7
#define PCIE_ESM_CAP_7__ESM_25P0G__SHIFT                                                                      0x0
#define PCIE_ESM_CAP_7__ESM_25P1G__SHIFT                                                                      0x1
#define PCIE_ESM_CAP_7__ESM_25P2G__SHIFT                                                                      0x2
#define PCIE_ESM_CAP_7__ESM_25P3G__SHIFT                                                                      0x3
#define PCIE_ESM_CAP_7__ESM_25P4G__SHIFT                                                                      0x4
#define PCIE_ESM_CAP_7__ESM_25P5G__SHIFT                                                                      0x5
#define PCIE_ESM_CAP_7__ESM_25P6G__SHIFT                                                                      0x6
#define PCIE_ESM_CAP_7__ESM_25P7G__SHIFT                                                                      0x7
#define PCIE_ESM_CAP_7__ESM_25P8G__SHIFT                                                                      0x8
#define PCIE_ESM_CAP_7__ESM_25P9G__SHIFT                                                                      0x9
#define PCIE_ESM_CAP_7__ESM_26P0G__SHIFT                                                                      0xa
#define PCIE_ESM_CAP_7__ESM_26P1G__SHIFT                                                                      0xb
#define PCIE_ESM_CAP_7__ESM_26P2G__SHIFT                                                                      0xc
#define PCIE_ESM_CAP_7__ESM_26P3G__SHIFT                                                                      0xd
#define PCIE_ESM_CAP_7__ESM_26P4G__SHIFT                                                                      0xe
#define PCIE_ESM_CAP_7__ESM_26P5G__SHIFT                                                                      0xf
#define PCIE_ESM_CAP_7__ESM_26P6G__SHIFT                                                                      0x10
#define PCIE_ESM_CAP_7__ESM_26P7G__SHIFT                                                                      0x11
#define PCIE_ESM_CAP_7__ESM_26P8G__SHIFT                                                                      0x12
#define PCIE_ESM_CAP_7__ESM_26P9G__SHIFT                                                                      0x13
#define PCIE_ESM_CAP_7__ESM_27P0G__SHIFT                                                                      0x14
#define PCIE_ESM_CAP_7__ESM_27P1G__SHIFT                                                                      0x15
#define PCIE_ESM_CAP_7__ESM_27P2G__SHIFT                                                                      0x16
#define PCIE_ESM_CAP_7__ESM_27P3G__SHIFT                                                                      0x17
#define PCIE_ESM_CAP_7__ESM_27P4G__SHIFT                                                                      0x18
#define PCIE_ESM_CAP_7__ESM_27P5G__SHIFT                                                                      0x19
#define PCIE_ESM_CAP_7__ESM_27P6G__SHIFT                                                                      0x1a
#define PCIE_ESM_CAP_7__ESM_27P7G__SHIFT                                                                      0x1b
#define PCIE_ESM_CAP_7__ESM_27P8G__SHIFT                                                                      0x1c
#define PCIE_ESM_CAP_7__ESM_27P9G__SHIFT                                                                      0x1d
#define PCIE_ESM_CAP_7__ESM_28P0G__SHIFT                                                                      0x1e
#define PCIE_ESM_CAP_7__ESM_25P0G_MASK                                                                        0x00000001L
#define PCIE_ESM_CAP_7__ESM_25P1G_MASK                                                                        0x00000002L
#define PCIE_ESM_CAP_7__ESM_25P2G_MASK                                                                        0x00000004L
#define PCIE_ESM_CAP_7__ESM_25P3G_MASK                                                                        0x00000008L
#define PCIE_ESM_CAP_7__ESM_25P4G_MASK                                                                        0x00000010L
#define PCIE_ESM_CAP_7__ESM_25P5G_MASK                                                                        0x00000020L
#define PCIE_ESM_CAP_7__ESM_25P6G_MASK                                                                        0x00000040L
#define PCIE_ESM_CAP_7__ESM_25P7G_MASK                                                                        0x00000080L
#define PCIE_ESM_CAP_7__ESM_25P8G_MASK                                                                        0x00000100L
#define PCIE_ESM_CAP_7__ESM_25P9G_MASK                                                                        0x00000200L
#define PCIE_ESM_CAP_7__ESM_26P0G_MASK                                                                        0x00000400L
#define PCIE_ESM_CAP_7__ESM_26P1G_MASK                                                                        0x00000800L
#define PCIE_ESM_CAP_7__ESM_26P2G_MASK                                                                        0x00001000L
#define PCIE_ESM_CAP_7__ESM_26P3G_MASK                                                                        0x00002000L
#define PCIE_ESM_CAP_7__ESM_26P4G_MASK                                                                        0x00004000L
#define PCIE_ESM_CAP_7__ESM_26P5G_MASK                                                                        0x00008000L
#define PCIE_ESM_CAP_7__ESM_26P6G_MASK                                                                        0x00010000L
#define PCIE_ESM_CAP_7__ESM_26P7G_MASK                                                                        0x00020000L
#define PCIE_ESM_CAP_7__ESM_26P8G_MASK                                                                        0x00040000L
#define PCIE_ESM_CAP_7__ESM_26P9G_MASK                                                                        0x00080000L
#define PCIE_ESM_CAP_7__ESM_27P0G_MASK                                                                        0x00100000L
#define PCIE_ESM_CAP_7__ESM_27P1G_MASK                                                                        0x00200000L
#define PCIE_ESM_CAP_7__ESM_27P2G_MASK                                                                        0x00400000L
#define PCIE_ESM_CAP_7__ESM_27P3G_MASK                                                                        0x00800000L
#define PCIE_ESM_CAP_7__ESM_27P4G_MASK                                                                        0x01000000L
#define PCIE_ESM_CAP_7__ESM_27P5G_MASK                                                                        0x02000000L
#define PCIE_ESM_CAP_7__ESM_27P6G_MASK                                                                        0x04000000L
#define PCIE_ESM_CAP_7__ESM_27P7G_MASK                                                                        0x08000000L
#define PCIE_ESM_CAP_7__ESM_27P8G_MASK                                                                        0x10000000L
#define PCIE_ESM_CAP_7__ESM_27P9G_MASK                                                                        0x20000000L
#define PCIE_ESM_CAP_7__ESM_28P0G_MASK                                                                        0x40000000L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_0_COMMAND
#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF0_0_STATUS
#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_0_LATENCY
#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF0_0_HEADER
#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_0_BIST
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0x000000FFL
//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF0_0_PMI_CAP
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
//BIF_CFG_DEV0_EPF0_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RESERVED_MASK                                                          0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                  0x4
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                    0x0010L
#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                      0x0020L
//BIF_CFG_DEV0_EPF0_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_0_SLOT_CAP2__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_SLOT_CNTL2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_SLOT_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0x0000FFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0x0000FFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x1FL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__RESERVED_MASK                                                    0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                             0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0x00FFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK     0x00000007L
#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x00000001L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x00000002L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK                       0x000000FFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK                       0x0000FF00L
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
//BIF_CFG_DEV0_EPF1_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_0_COMMAND
#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF1_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF1_0_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF1_0_STATUS
#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF1_0_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF1_0_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF1_0_STATUS__PCI_66_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV0_EPF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF1_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF1_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF1_0_REVISION_ID
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF1_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF1_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF1_0_LATENCY
#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF1_0_HEADER
#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF1_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF1_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF1_0_BIST
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF1_0_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_CAP_PTR
#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_0_CAP_PTR__CAP_PTR_MASK                                                             0x000000FFL
//BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF1_0_MIN_GRANT
#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF1_0_MAX_LATENCY
#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF1_0_PMI_CAP
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF1_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
//BIF_CFG_DEV0_EPF1_0_LINK_CAP
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF1_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
//BIF_CFG_DEV0_EPF1_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF1_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF1_0_LINK_CAP2__RESERVED_MASK                                                          0xFFFFFE00L
//BIF_CFG_DEV0_EPF1_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF1_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                  0x4
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                    0x0010L
#define BIF_CFG_DEV0_EPF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                      0x0020L
//BIF_CFG_DEV0_EPF1_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_0_SLOT_CAP2__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_SLOT_CNTL2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_SLOT_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0x0000FFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MASK
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0x0000FFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF1_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x1FL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3__RESERVED_MASK                                                    0xFFFFFFFCL
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                             0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
//BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
//BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0x00FFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK     0x00000007L
#define BIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x00000001L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x00000002L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK                       0x000000FFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK                       0x0000FF00L
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
//BIF_CFG_DEV0_SWDS0_VENDOR_ID
#define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_VENDOR_ID__VENDOR_ID_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_SWDS0_DEVICE_ID
#define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_ID__DEVICE_ID_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_SWDS0_COMMAND
#define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN__SHIFT                                                            0x0
#define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN__SHIFT                                                           0x1
#define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN__SHIFT                                                      0x2
#define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN__SHIFT                                                       0x5
#define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                              0x6
#define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING__SHIFT                                                        0x7
#define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN__SHIFT                                                            0x8
#define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN__SHIFT                                                        0x9
#define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS__SHIFT                                                            0xa
#define BIF_CFG_DEV0_SWDS0_COMMAND__IOEN_DN_MASK                                                              0x0001L
#define BIF_CFG_DEV0_SWDS0_COMMAND__MEMEN_DN_MASK                                                             0x0002L
#define BIF_CFG_DEV0_SWDS0_COMMAND__BUS_MASTER_EN_MASK                                                        0x0004L
#define BIF_CFG_DEV0_SWDS0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_SWDS0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_SWDS0_COMMAND__PAL_SNOOP_EN_MASK                                                         0x0020L
#define BIF_CFG_DEV0_SWDS0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                0x0040L
#define BIF_CFG_DEV0_SWDS0_COMMAND__AD_STEPPING_MASK                                                          0x0080L
#define BIF_CFG_DEV0_SWDS0_COMMAND__SERR_EN_MASK                                                              0x0100L
#define BIF_CFG_DEV0_SWDS0_COMMAND__FAST_B2B_EN_MASK                                                          0x0200L
#define BIF_CFG_DEV0_SWDS0_COMMAND__INT_DIS_MASK                                                              0x0400L
//BIF_CFG_DEV0_SWDS0_STATUS
#define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS__SHIFT                                                          0x3
#define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST__SHIFT                                                            0x4
#define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_EN__SHIFT                                                           0x5
#define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                            0x8
#define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING__SHIFT                                                       0x9
#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                 0xb
#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                               0xc
#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                               0xd
#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                               0xe
#define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                               0xf
#define BIF_CFG_DEV0_SWDS0_STATUS__INT_STATUS_MASK                                                            0x0008L
#define BIF_CFG_DEV0_SWDS0_STATUS__CAP_LIST_MASK                                                              0x0010L
#define BIF_CFG_DEV0_SWDS0_STATUS__PCI_66_EN_MASK                                                             0x0020L
#define BIF_CFG_DEV0_SWDS0_STATUS__FAST_BACK_CAPABLE_MASK                                                     0x0080L
#define BIF_CFG_DEV0_SWDS0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                              0x0100L
#define BIF_CFG_DEV0_SWDS0_STATUS__DEVSEL_TIMING_MASK                                                         0x0600L
#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                   0x0800L
#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                 0x1000L
#define BIF_CFG_DEV0_SWDS0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                 0x2000L
#define BIF_CFG_DEV0_SWDS0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                 0x4000L
#define BIF_CFG_DEV0_SWDS0_STATUS__PARITY_ERROR_DETECTED_MASK                                                 0x8000L
//BIF_CFG_DEV0_SWDS0_REVISION_ID
#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                   0x4
#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MINOR_REV_ID_MASK                                                     0x0FL
#define BIF_CFG_DEV0_SWDS0_REVISION_ID__MAJOR_REV_ID_MASK                                                     0xF0L
//BIF_CFG_DEV0_SWDS0_PROG_INTERFACE
#define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                0xFFL
//BIF_CFG_DEV0_SWDS0_SUB_CLASS
#define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_SUB_CLASS__SUB_CLASS_MASK                                                          0xFFL
//BIF_CFG_DEV0_SWDS0_BASE_CLASS
#define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_BASE_CLASS__BASE_CLASS_MASK                                                        0xFFL
//BIF_CFG_DEV0_SWDS0_CACHE_LINE
#define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_SWDS0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                   0xFFL
//BIF_CFG_DEV0_SWDS0_LATENCY
#define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_LATENCY__LATENCY_TIMER_MASK                                                        0xFFL
//BIF_CFG_DEV0_SWDS0_HEADER
#define BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE__SHIFT                                                         0x0
#define BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE__SHIFT                                                         0x7
#define BIF_CFG_DEV0_SWDS0_HEADER__HEADER_TYPE_MASK                                                           0x7FL
#define BIF_CFG_DEV0_SWDS0_HEADER__DEVICE_TYPE_MASK                                                           0x80L
//BIF_CFG_DEV0_SWDS0_BIST
#define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP__SHIFT                                                             0x0
#define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT__SHIFT                                                             0x6
#define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP__SHIFT                                                              0x7
#define BIF_CFG_DEV0_SWDS0_BIST__BIST_COMP_MASK                                                               0x0FL
#define BIF_CFG_DEV0_SWDS0_BIST__BIST_STRT_MASK                                                               0x40L
#define BIF_CFG_DEV0_SWDS0_BIST__BIST_CAP_MASK                                                                0x80L
//BIF_CFG_DEV0_SWDS0_BASE_ADDR_1
#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_BASE_ADDR_1__BASE_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                       0x8
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                         0x10
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                             0x18
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                           0x000000FFL
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                         0x0000FF00L
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                           0x00FF0000L
#define BIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                               0xFF000000L
//BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                0x8
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                     0xc
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                   0x000FL
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_BASE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                  0x0F00L
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                       0xF000L
//BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__CAP_LIST__SHIFT                                                  0x4
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                         0x7
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                  0x8
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                             0x9
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                       0xb
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                     0xc
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                     0xd
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                     0xe
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__CAP_LIST_MASK                                                    0x0010L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PCI_66_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                           0x0080L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                    0x0100L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                               0x0600L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                         0x0800L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                       0x1000L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                       0x2000L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                       0x4000L
#define BIF_CFG_DEV0_SWDS0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                              0x4
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                              0x10
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                             0x14
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                0x0000FFF0L
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                        0x4
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                        0x10
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                           0x0000000FL
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                          0x0000FFF0L
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER
#define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                          0x0
#define BIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                            0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                            0x10
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                              0xFFFF0000L
//BIF_CFG_DEV0_SWDS0_CAP_PTR
#define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR__SHIFT                                                            0x0
#define BIF_CFG_DEV0_SWDS0_CAP_PTR__CAP_PTR_MASK                                                              0x000000FFL
//BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE
#define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                0xFFL
//BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN
#define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                  0xFFL
//BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                    0x1
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                    0x4
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                          0x5
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                        0x6
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                0x7
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                           0x0001L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                      0x0002L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                      0x0010L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                            0x0020L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                          0x0040L
#define BIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                  0x0080L
//BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_SWDS0_PMI_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_SWDS0_PMI_CAP
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK__SHIFT                                                          0x3
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                  0x5
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT__SHIFT                                                         0x9
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT__SHIFT                                                        0xb
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__VERSION_MASK                                                              0x0007L
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_CLOCK_MASK                                                            0x0008L
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                    0x0020L
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__AUX_CURRENT_MASK                                                          0x01C0L
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D1_SUPPORT_MASK                                                           0x0200L
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__D2_SUPPORT_MASK                                                           0x0400L
#define BIF_CFG_DEV0_SWDS0_PMI_CAP__PME_SUPPORT_MASK                                                          0xF800L
//BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                              0x3
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                     0x8
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                0x9
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                 0xf
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                              0x16
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                 0x17
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                   0x18
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                0x00000008L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_EN_MASK                                                       0x00000100L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                  0x00001E00L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                   0x00006000L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                   0x00008000L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                0x00400000L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                   0x00800000L
#define BIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                     0xFF000000L
//BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_SWDS0_PCIE_CAP
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                       0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                  0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                   0x9
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__VERSION_MASK                                                             0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__DEVICE_TYPE_MASK                                                         0x00F0L
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                    0x0100L
#define BIF_CFG_DEV0_SWDS0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                     0x3E00L
//BIF_CFG_DEV0_SWDS0_DEVICE_CAP
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                    0x3
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                    0x5
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                          0x6
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                           0x9
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                        0xf
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                       0x12
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                       0x1a
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                     0x1c
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                               0x00000007L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                      0x00000018L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__EXTENDED_TAG_MASK                                                      0x00000020L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                            0x000001C0L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                             0x00000E00L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                          0x00008000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                         0x03FC0000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                         0x0C000000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP__FLR_CAPABLE_MASK                                                       0x10000000L
//BIF_CFG_DEV0_SWDS0_DEVICE_CNTL
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                    0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                               0x1
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                   0x2
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                               0x5
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                0x8
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                0x9
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                0xa
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                    0xb
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                          0xc
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                            0xf
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                      0x0001L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                 0x0002L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                     0x0004L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                   0x0010L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                 0x00E0L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                  0x0100L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                  0x0200L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                  0x0400L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                      0x0800L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                            0x7000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                              0x8000L
//BIF_CFG_DEV0_SWDS0_DEVICE_STATUS
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                0x1
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                    0x2
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                 0x3
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR__SHIFT                                                      0x4
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                            0x5
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__CORR_ERR_MASK                                                       0x0001L
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                  0x0002L
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__FATAL_ERR_MASK                                                      0x0004L
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__USR_DETECTED_MASK                                                   0x0008L
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__AUX_PWR_MASK                                                        0x0010L
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                              0x0020L
//BIF_CFG_DEV0_SWDS0_LINK_CAP
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH__SHIFT                                                        0x4
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                  0xc
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                   0xf
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                            0x12
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                       0x13
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                          0x15
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                       0x16
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER__SHIFT                                                       0x18
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_SPEED_MASK                                                          0x0000000FL
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_WIDTH_MASK                                                          0x000003F0L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PM_SUPPORT_MASK                                                          0x00000C00L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                    0x00007000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                              0x00040000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                         0x00080000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                         0x00100000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                            0x00200000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                         0x00400000L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP__PORT_NUMBER_MASK                                                         0xFF000000L
//BIF_CFG_DEV0_SWDS0_LINK_CNTL
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL__SHIFT                                                       0x0
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                0x3
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS__SHIFT                                                         0x4
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                     0x5
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                 0x6
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                    0x7
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                        0x8
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                      0x9
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                        0xa
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                        0xb
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__PM_CONTROL_MASK                                                         0x0003L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                  0x0008L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_DIS_MASK                                                           0x0010L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__RETRAIN_LINK_MASK                                                       0x0020L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                   0x0040L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__EXTENDED_SYNC_MASK                                                      0x0080L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                          0x0100L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                        0x0200L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                          0x0400L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                          0x0800L
//BIF_CFG_DEV0_SWDS0_LINK_STATUS
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                          0x4
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING__SHIFT                                                  0xb
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                 0xc
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE__SHIFT                                                      0xd
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                      0xe
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                      0xf
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                               0x000FL
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                            0x03F0L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_TRAINING_MASK                                                    0x0800L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                   0x1000L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__DL_ACTIVE_MASK                                                        0x2000L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                        0x4000L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                        0x8000L
//BIF_CFG_DEV0_SWDS0_SLOT_CAP
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                            0x1
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                0x2
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                            0x3
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                             0x4
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                  0x5
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                   0x6
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                              0x7
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                              0xf
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                    0x12
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                 0x13
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                 0x00000001L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                              0x00000002L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                  0x00000004L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                              0x00000008L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                               0x00000010L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                    0x00000020L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                     0x00000040L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                0x00007F80L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                0x00018000L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                       0x00020000L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                      0x00040000L
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                   0xFFF80000L
//BIF_CFG_DEV0_SWDS0_SLOT_CNTL
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                           0x0
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                            0x1
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                            0x2
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                       0x3
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                              0x6
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                               0x8
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                              0xa
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                       0xb
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                              0xc
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                             0x0001L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                              0x0002L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                              0x0004L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                         0x0008L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                0x00C0L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                 0x0300L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                0x0400L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                         0x0800L
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                0x1000L
//BIF_CFG_DEV0_SWDS0_SLOT_STATUS
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                             0x1
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                             0x2
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                        0x3
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                              0x4
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                               0x5
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                          0x6
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                   0x7
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                               0x8
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                              0x0001L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                               0x0002L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                               0x0004L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                          0x0008L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                0x0010L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                 0x0020L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                            0x0040L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                     0x0080L
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                 0x0100L
//BIF_CFG_DEV0_SWDS0_DEVICE_CAP2
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                    0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                      0x4
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                       0x5
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                     0x6
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                     0x7
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                     0x8
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                         0x9
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                      0xa
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                  0xb
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                             0xc
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                 0x12
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                   0x14
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                   0x15
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                       0x16
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                      0x0000000FL
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                        0x00000010L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                         0x00000020L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                       0x00000040L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                       0x00000080L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                       0x00000100L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                           0x00000200L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                        0x00000400L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                    0x00000800L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                               0x00003000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                   0x000C0000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                     0x00100000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                     0x00200000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                         0x00C00000L
//BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                               0x4
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                             0x5
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                      0x7
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                            0x8
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                         0x9
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN__SHIFT                                                        0xa
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                       0xd
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                               0x000FL
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                 0x0010L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                               0x0020L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                             0x0040L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                        0x0080L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                              0x0100L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                           0x0200L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__LTR_EN_MASK                                                          0x0400L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__OBFF_EN_MASK                                                         0x6000L
#define BIF_CFG_DEV0_SWDS0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                     0x8000L
//BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_SWDS0_DEVICE_STATUS2__RESERVED_MASK                                                      0xFFFFL
//BIF_CFG_DEV0_SWDS0_LINK_CAP2
#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                             0x1
#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                              0x8
#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RESERVED__SHIFT                                                         0x9
#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                               0x000000FEL
#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                0x00000100L
#define BIF_CFG_DEV0_SWDS0_LINK_CAP2__RESERVED_MASK                                                           0xFFFFFE00L
//BIF_CFG_DEV0_SWDS0_LINK_CNTL2
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                0x4
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                     0x5
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                           0x6
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                     0x7
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                            0xa
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                  0xb
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                           0xc
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                 0x000FL
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                  0x0010L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                       0x0020L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                             0x0040L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__XMIT_MARGIN_MASK                                                       0x0380L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                              0x0400L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                    0x0800L
#define BIF_CFG_DEV0_SWDS0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                             0xF000L
//BIF_CFG_DEV0_SWDS0_LINK_STATUS2
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                          0x0
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                         0x1
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                   0x2
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                   0x3
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                   0x4
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                            0x0001L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                           0x0002L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                     0x0004L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                     0x0008L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                     0x0010L
#define BIF_CFG_DEV0_SWDS0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                       0x0020L
//BIF_CFG_DEV0_SWDS0_SLOT_CAP2
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_SWDS0_SLOT_CAP2__RESERVED_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_SLOT_CNTL2
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_SLOT_CNTL2__RESERVED_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_SWDS0_SLOT_STATUS2
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_SLOT_STATUS2__RESERVED_MASK                                                        0xFFFFL
//BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_SWDS0_MSI_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                 0x1
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                     0x7
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                     0x8
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                   0x000EL
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                    0x0070L
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                       0x0080L
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                       0x0100L
//BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                            0x2
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                              0xFFFFFFFCL
//BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA__MSI_DATA_MASK                                                        0x0000FFFFL
//BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_SWDS0_SSID_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_SWDS0_SSID_CAP
#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                      0x10
#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_SSID_CAP__SUBSYSTEM_ID_MASK                                                        0xFFFF0000L
//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                          0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                            0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                              0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                            0xa
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                           0x00000007L
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                              0x00000070L
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                0x00000300L
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                              0x00000C00L
//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                            0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                              0x000EL
//BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                      0x0001L
//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                       0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                           0x000000FFL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                     0x00008000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                         0x003F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                  0xFF000000L
//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                     0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                 0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                               0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                           0x1f
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                         0x00000001L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                       0x000000FEL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                   0x00010000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                       0x000E0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                 0x07000000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                             0x80000000L
//BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                             0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                            0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                               0x0001L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                              0x0002L
//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                       0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                           0x000000FFL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                     0x00008000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                         0x003F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                  0xFF000000L
//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                     0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                 0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                               0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                           0x1f
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                         0x00000001L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                       0x000000FEL
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                   0x00010000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                       0x000E0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                 0x07000000L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                             0x80000000L
//BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                             0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                            0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                               0x0001L
#define BIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                              0x0002L
//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                     0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                     0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                      0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                   0x5
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                      0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                       0xd
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                    0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                      0x12
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                     0x13
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                               0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                0x15
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                               0x16
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                               0x17
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                      0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                       0x19
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                        0x00000010L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                     0x00000020L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                        0x00001000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                         0x00002000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                    0x00004000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                  0x00008000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                      0x00010000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                       0x00020000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                        0x00040000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                       0x00080000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                 0x00100000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                  0x00200000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                 0x00400000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                 0x00800000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                        0x01000000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                         0x02000000L
//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                          0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                       0x5
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                          0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                           0xd
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                        0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                         0x11
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                          0x12
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                         0x13
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                   0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                    0x15
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                   0x16
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                   0x17
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                          0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                           0x19
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                            0x00000010L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                         0x00000020L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                            0x00001000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                             0x00002000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                        0x00004000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                      0x00008000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                          0x00010000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                           0x00020000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                            0x00040000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                           0x00080000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                     0x00100000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                      0x00200000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                     0x00400000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                     0x00800000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                            0x01000000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                             0x02000000L
//BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                  0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                               0x5
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                  0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                   0xd
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                              0xe
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                            0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                 0x11
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                  0x12
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                 0x13
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                           0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                            0x15
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                           0x16
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                           0x17
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                  0x18
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                   0x19
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                    0x00000010L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                 0x00000020L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                    0x00001000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                     0x00002000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                0x00004000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                              0x00008000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                  0x00010000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                   0x00020000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                    0x00040000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                   0x00080000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                             0x00100000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                              0x00200000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                             0x00400000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                             0x00800000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                    0x01000000L
#define BIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                     0x02000000L
//BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                        0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                        0x6
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                       0x7
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                            0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                           0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                          0xd
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                          0x00000001L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                          0x00000040L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                         0x00000080L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                              0x00000100L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                             0x00001000L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                            0x00002000L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                     0x00008000L
//BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                            0x6
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                           0x7
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                               0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                              0xd
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                       0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                              0x00000001L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                              0x00000040L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                             0x00000080L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                  0x00000100L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                 0x00001000L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                0x00002000L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                         0x00008000L
//BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                        0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                         0x5
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                       0x7
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                        0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                   0x9
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                    0xa
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                               0xb
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                          0x0000001FL
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                           0x00000020L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                            0x00000040L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                         0x00000080L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                          0x00000100L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                     0x00000200L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                      0x00000400L
#define BIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                 0x00000800L
//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                               0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                   0x2
#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                         0x00000001L
#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                 0x00000002L
#define BIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3__RESERVED_MASK                                                     0xFFFFFFFCL
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                              0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                            0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                              0xFFFF0000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                          0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                          0x2
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                       0x3
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                           0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                            0x5
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                         0x6
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                    0x8
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                               0x0001L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                            0x0002L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                            0x0004L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                         0x0008L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                             0x0010L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                              0x0020L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                           0x0040L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                      0xFF00L
//BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                      0x2
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                   0x3
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                           0x0001L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                        0x0004L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                     0x0008L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                       0x0040L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF0_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF0_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF0_0_BIST
#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF0_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF1_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF1_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF1_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF1_0_BIST
#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF1_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF2_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF2_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF2_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF2_0_BIST
#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF2_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF3_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF3_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF3_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF3_0_BIST
#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF3_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF4_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF4_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF4_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF4_0_BIST
#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF4_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF5_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF5_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF5_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF5_0_BIST
#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF5_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF6_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF6_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF6_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF6_0_BIST
#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF6_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF7_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF7_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF7_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF7_0_BIST
#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF7_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF8_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF8_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF8_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF8_0_BIST
#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF8_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_0_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF9_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF9_0_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF9_0_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF9_0_BIST
#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF9_0_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_0_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF10_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF10_0_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF10_0_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF10_0_BIST
#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF10_0_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_0_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF11_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF11_0_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF11_0_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF11_0_BIST
#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF11_0_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_0_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF12_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF12_0_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF12_0_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF12_0_BIST
#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF12_0_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_0_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF13_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF13_0_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF13_0_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF13_0_BIST
#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF13_0_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_0_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF14_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF14_0_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF14_0_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF14_0_BIST
#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF14_0_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_COMMAND
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_0_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF15_0_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF15_0_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_LATENCY
#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_HEADER
#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF15_0_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF15_0_BIST
#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF15_0_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767]
//MM_INDEX
#define MM_INDEX__MM_OFFSET__SHIFT                                                                            0x0
#define MM_INDEX__MM_APER__SHIFT                                                                              0x1f
#define MM_INDEX__MM_OFFSET_MASK                                                                              0x7FFFFFFFL
#define MM_INDEX__MM_APER_MASK                                                                                0x80000000L
//MM_DATA
#define MM_DATA__MM_DATA__SHIFT                                                                               0x0
#define MM_DATA__MM_DATA_MASK                                                                                 0xFFFFFFFFL
//MM_INDEX_HI
#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                                      0x0
#define MM_INDEX_HI__MM_OFFSET_HI_MASK                                                                        0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767]
//SYSHUB_INDEX_OVLP
#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT                                                               0x0
#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK                                                                 0x003FFFFFL
//SYSHUB_DATA_OVLP
#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT                                                                  0x0
#define SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK                                                                    0xFFFFFFFFL
//PCIE_INDEX
#define PCIE_INDEX__PCIE_INDEX__SHIFT                                                                         0x0
#define PCIE_INDEX__PCIE_INDEX_MASK                                                                           0xFFFFFFFFL
//PCIE_DATA
#define PCIE_DATA__PCIE_DATA__SHIFT                                                                           0x0
#define PCIE_DATA__PCIE_DATA_MASK                                                                             0xFFFFFFFFL
//PCIE_INDEX2
#define PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                                       0x0
#define PCIE_INDEX2__PCIE_INDEX2_MASK                                                                         0xFFFFFFFFL
//PCIE_DATA2
#define PCIE_DATA2__PCIE_DATA2__SHIFT                                                                         0x0
#define PCIE_DATA2__PCIE_DATA2_MASK                                                                           0xFFFFFFFFL
//SBIOS_SCRATCH_0
#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                              0x0
#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                                0xFFFFFFFFL
//SBIOS_SCRATCH_1
#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                              0x0
#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                                0xFFFFFFFFL
//SBIOS_SCRATCH_2
#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                              0x0
#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                                0xFFFFFFFFL
//SBIOS_SCRATCH_3
#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                              0x0
#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                                0xFFFFFFFFL
//BIOS_SCRATCH_0
#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                                 0x0
#define BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_1
#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                                 0x0
#define BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_2
#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                                 0x0
#define BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_3
#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                                 0x0
#define BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_4
#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                                 0x0
#define BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_5
#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                                 0x0
#define BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_6
#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                                 0x0
#define BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_7
#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                                 0x0
#define BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_8
#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                                 0x0
#define BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_9
#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                                 0x0
#define BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                                   0xFFFFFFFFL
//BIOS_SCRATCH_10
#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                               0x0
#define BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                                 0xFFFFFFFFL
//BIOS_SCRATCH_11
#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                               0x0
#define BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                                 0xFFFFFFFFL
//BIOS_SCRATCH_12
#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                               0x0
#define BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                                 0xFFFFFFFFL
//BIOS_SCRATCH_13
#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                               0x0
#define BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                                 0xFFFFFFFFL
//BIOS_SCRATCH_14
#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                               0x0
#define BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                                 0xFFFFFFFFL
//BIOS_SCRATCH_15
#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                               0x0
#define BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                                 0xFFFFFFFFL
//BIF_RLC_INTR_CNTL
#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                            0x0
#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                                     0x1
#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                           0x2
#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                                      0x3
#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                              0x00000001L
#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                                       0x00000002L
#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                             0x00000004L
#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                                        0x00000008L
//BIF_VCE_INTR_CNTL
#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                            0x0
#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                                     0x1
#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                           0x2
#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                                      0x3
#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                              0x00000001L
#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                                       0x00000002L
#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                             0x00000004L
#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                                        0x00000008L
//BIF_UVD_INTR_CNTL
#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                            0x0
#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                                     0x1
#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                           0x2
#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                                      0x3
#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                              0x00000001L
#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                                       0x00000002L
#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                             0x00000004L
#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                                        0x00000008L
//GFX_MMIOREG_CAM_ADDR0
#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR0
#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR1
#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR1
#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR2
#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR2
#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR3
#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR3
#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR4
#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR4
#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR5
#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR5
#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR6
#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR6
#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_ADDR7
#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                                 0x000FFFFFL
//GFX_MMIOREG_CAM_REMAP_ADDR7
#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                                   0x0
#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                                     0x000FFFFFL
//GFX_MMIOREG_CAM_CNTL
#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                               0x0
#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                                 0x000000FFL
//GFX_MMIOREG_CAM_ZERO_CPL
#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                         0x0
#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                           0xFFFFFFFFL
//GFX_MMIOREG_CAM_ONE_CPL
#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                           0x0
#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                             0xFFFFFFFFL
//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                         0x0
#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                           0xFFFFFFFFL


// addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39]
//SYSHUB_INDEX
#define SYSHUB_INDEX__INDEX__SHIFT                                                                            0x0
#define SYSHUB_INDEX__INDEX_MASK                                                                              0xFFFFFFFFL
//SYSHUB_DATA
#define SYSHUB_DATA__DATA__SHIFT                                                                              0x0
#define SYSHUB_DATA__DATA_MASK                                                                                0xFFFFFFFFL


// addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
//RCC_BIF_STRAP0
#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                               0x7
#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                                 0x00000080L

//RCC_DEV0_EPF0_STRAP0
#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                                  0x0
#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                               0x10
#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                               0x14
#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                                 0x18
#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                                    0x1c
#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                                      0x1d
#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                                 0x1e
#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                                 0x1f
#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                                    0x0000FFFFL
#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                                 0x000F0000L
#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                                 0x00F00000L
#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                                   0x0F000000L
#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                                      0x10000000L
#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                                        0x20000000L
#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                                   0x40000000L
#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                                   0x80000000L


// addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975]
//EP_PCIE_SCRATCH
#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                                  0x0
#define EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                                    0xFFFFFFFFL
//EP_PCIE_CNTL
#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                                0x7
#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                                          0x8
#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                             0x1e
#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                                  0x00000080L
#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                            0x00000100L
#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                               0x40000000L
//EP_PCIE_INT_CNTL
#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                              0x0
#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                                         0x1
#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                                             0x2
#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                                          0x3
#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                              0x4
#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                                       0x6
#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                                0x00000001L
#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                                           0x00000002L
#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                               0x00000004L
#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                                            0x00000008L
#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                                0x00000010L
#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                                         0x00000040L
//EP_PCIE_INT_STATUS
#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                                        0x0
#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                                   0x1
#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                                       0x2
#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                                    0x3
#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                                        0x4
#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                                 0x6
#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                                          0x00000001L
#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                                     0x00000002L
#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                                         0x00000004L
#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                                      0x00000008L
#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                                          0x00000010L
#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                                   0x00000040L
//EP_PCIE_RX_CNTL2
#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                                 0x0
#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                                   0x00000001L
//EP_PCIE_BUS_CNTL
#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                            0x7
#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                              0x00000080L
//EP_PCIE_CFG_CNTL
#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                                     0x0
#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                                0x1
#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                                0x2
#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                                       0x00000001L
#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                                  0x00000002L
#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                                  0x00000004L
//EP_PCIE_TX_LTR_CNTL
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                                    0x0
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                                     0x3
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                                    0x6
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                                   0x7
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                                    0xa
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                                   0xd
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                                             0xe
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                               0xf
#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                                          0x10
#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                                 0x11
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                                      0x00000007L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                                       0x00000038L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                                      0x00000040L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                                     0x00000380L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                                      0x00001C00L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                                     0x00002000L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                               0x00004000L
#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                                 0x00008000L
#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                                            0x00010000L
#define EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                                   0x00020000L
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//EP_PCIE_F0_DPA_CAP
#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                             0x8
#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                            0xc
#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                            0x10
#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                            0x18
#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                               0x00000300L
#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                              0x00003000L
#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                              0x00FF0000L
#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                              0xFF000000L
//EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                                     0x0
#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                                       0xFFL
//EP_PCIE_F0_DPA_CNTL
#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                                           0x0
#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                                       0x8
#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                                             0x001FL
#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                                         0x0100L
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                                           0x0
#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                             0xFFL
//EP_PCIE_PME_CONTROL
#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                                         0x0
#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                                           0x1FL
//EP_PCIEP_RESERVED
#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                              0x0
#define EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                                0xFFFFFFFFL
//EP_PCIE_TX_CNTL
#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                               0xa
#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                                0xc
#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                                 0x18
#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                                 0x19
#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                                 0x1a
#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                                 0x00000C00L
#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                                  0x00003000L
#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                                   0x01000000L
#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                                   0x02000000L
#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                                   0x04000000L
//EP_PCIE_TX_REQUESTER_ID
#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                              0x0
#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                                0x3
#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                   0x8
#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                                0x00000007L
#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                                  0x000000F8L
#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                     0x0000FF00L
//EP_PCIE_ERR_CNTL
#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                            0x0
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                          0x8
#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                     0x11
#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                             0x12
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                                 0x18
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                                 0x19
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                                 0x1a
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                                 0x1b
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                                 0x1c
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                                 0x1d
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                                 0x1e
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                                 0x1f
#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                              0x00000001L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                            0x00000700L
#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                       0x00020000L
#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                               0x00040000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                   0x01000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                                   0x02000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                                   0x04000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                                   0x08000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                                   0x10000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                                   0x20000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                                   0x40000000L
#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                                   0x80000000L
//EP_PCIE_RX_CNTL
#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                     0x8
#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                              0x9
#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                       0x14
#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                     0x15
#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                       0x16
#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                                    0x18
#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                        0x19
#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                                    0x1a
#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                       0x00000100L
#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                                0x00000200L
#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                         0x00100000L
#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                       0x00200000L
#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                         0x00400000L
#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                      0x01000000L
#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                          0x02000000L
#define EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                      0x04000000L
//EP_PCIE_LC_SPEED_CNTL
#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                        0x0
#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                        0x1
#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                          0x00000001L
#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                          0x00000002L


// addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975]
//DN_PCIE_RESERVED
#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                                0x0
#define DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                                  0xFFFFFFFFL
//DN_PCIE_SCRATCH
#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                                  0x0
#define DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                                    0xFFFFFFFFL
//DN_PCIE_CNTL
#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                                   0x0
#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                                             0x7
#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                             0x1e
#define DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                                     0x00000001L
#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                               0x00000080L
#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                               0x40000000L
//DN_PCIE_CONFIG_CNTL
#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                               0x19
#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                                 0x06000000L
//DN_PCIE_RX_CNTL2
#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                              0x1c
#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                                0x70000000L
//DN_PCIE_BUS_CNTL
#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                            0x7
#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                                  0x8
#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                              0x00000080L
#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                                    0x00000100L
//DN_PCIE_CFG_CNTL
#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                                     0x0
#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                                0x1
#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                                0x2
#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                                       0x00000001L
#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                                  0x00000002L
#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                                  0x00000004L


// addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975]
//PCIE_ERR_CNTL
#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                               0x0
#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                             0x8
#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                                    0xb
#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                        0x11
#define PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                                 0x00000001L
#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                               0x00000700L
#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                                      0x00000800L
#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                          0x00020000L
//PCIE_RX_CNTL
#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                        0x8
#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                                              0x9
#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                          0x14
#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                                     0x15
#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                           0x1b
#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                          0x00000100L
#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                                0x00000200L
#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                            0x00100000L
#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                                       0x00200000L
#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                             0x08000000L
//PCIE_LC_SPEED_CNTL
#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                           0x0
#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                           0x1
#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                             0x00000001L
#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                             0x00000002L
//PCIE_LC_CNTL2
#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                                     0x1b
#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                                       0x08000000L
//PCIEP_STRAP_MISC
#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                                          0xa
#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                                            0x00000400L
//LTR_MSG_INFO_FROM_EP
#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                                     0x0
#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                                       0xFFFFFFFFL


// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975]
//RCC_PF_0_0_RCC_ERR_LOG
#define RCC_PF_0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                                     0x0
#define RCC_PF_0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                            0x1
#define RCC_PF_0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                       0x00000001L
#define RCC_PF_0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                              0x00000002L
//RCC_PF_0_0_RCC_DOORBELL_APER_EN
#define RCC_PF_0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                          0x0
#define RCC_PF_0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                            0x00000001L
//RCC_PF_0_0_RCC_CONFIG_MEMSIZE
#define RCC_PF_0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                                  0x0
#define RCC_PF_0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                                    0xFFFFFFFFL
//RCC_PF_0_0_RCC_CONFIG_RESERVED
#define RCC_PF_0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                                0x0
#define RCC_PF_0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER
#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                            0x0
#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                                 0x1f
#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                              0x00000001L
#define RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                                   0x80000000L


// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975]
//RCC_ERR_INT_CNTL
#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT                                           0x0
#define RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK                                             0x00000001L
//RCC_BACO_CNTL_MISC
#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT                                                            0x0
#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT                                                             0x1
#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK                                                              0x00000001L
#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK                                                               0x00000002L
//RCC_RESET_EN
#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT                                                                 0xf
#define RCC_RESET_EN__DB_APER_RESET_EN_MASK                                                                   0x00008000L
//RCC_VDM_SUPPORT
#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                                  0x0
#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                                 0x1
#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                             0x2
#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                                   0x3
#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                               0x4
#define RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                                    0x00000001L
#define RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                                   0x00000002L
#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                               0x00000004L
#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                                     0x00000008L
#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                                 0x00000010L
//RCC_PEER_REG_RANGE0
#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT                                                                0x0
#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT                                                                  0x10
#define RCC_PEER_REG_RANGE0__START_ADDR_MASK                                                                  0x0000FFFFL
#define RCC_PEER_REG_RANGE0__END_ADDR_MASK                                                                    0xFFFF0000L
//RCC_PEER_REG_RANGE1
#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT                                                                0x0
#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT                                                                  0x10
#define RCC_PEER_REG_RANGE1__START_ADDR_MASK                                                                  0x0000FFFFL
#define RCC_PEER_REG_RANGE1__END_ADDR_MASK                                                                    0xFFFF0000L
//RCC_BUS_CNTL
#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                                       0x2
#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                                      0x3
#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                                       0x4
#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                                    0x5
#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                                   0x6
#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                                    0x7
#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                                   0x8
#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                            0xc
#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                                      0xd
#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                                     0x10
#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                                     0x11
#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                                     0x12
#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                                     0x13
#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                                     0x14
#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                                     0x15
#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                            0x18
#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                            0x19
#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                                       0x1c
#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                                       0x1d
#define RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                                         0x00000004L
#define RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                                        0x00000008L
#define RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                                         0x00000010L
#define RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                                      0x00000020L
#define RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                                     0x00000040L
#define RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                                      0x00000080L
#define RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                                     0x00000100L
#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                              0x00001000L
#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                                        0x00002000L
#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                                       0x00010000L
#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                                       0x00020000L
#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                                       0x00040000L
#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                                       0x00080000L
#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                                       0x00100000L
#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                                       0x00200000L
#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                              0x01000000L
#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                              0x0E000000L
#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                                         0x10000000L
#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                                         0xE0000000L
//RCC_CONFIG_CNTL
#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT                                                                0x0
#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT                                                          0x2
#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT                                                                   0x3
#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK                                                                  0x00000001L
#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK                                                            0x00000004L
#define RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK                                                                     0x00000018L
//RCC_CONFIG_F0_BASE
#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT                                                                    0x0
#define RCC_CONFIG_F0_BASE__F0_BASE_MASK                                                                      0xFFFFFFFFL
//RCC_CONFIG_APER_SIZE
#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT                                                                0x0
#define RCC_CONFIG_APER_SIZE__APER_SIZE_MASK                                                                  0xFFFFFFFFL
//RCC_CONFIG_REG_APER_SIZE
#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT                                                        0x0
#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK                                                          0x000FFFFFL
//RCC_XDMA_LO
#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT                                                              0x0
#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT                                                                  0x1f
#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK                                                                0x7FFFFFFFL
#define RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK                                                                    0x80000000L
//RCC_XDMA_HI
#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT                                                              0x0
#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK                                                                0x7FFFFFFFL
//RCC_FEATURES_CONTROL_MISC
#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT                                        0x4
#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT                                 0x5
#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT                                0x6
#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                              0x7
#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                            0x8
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                               0x9
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                               0xa
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                            0xb
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                             0xc
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                                 0xd
#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                                 0xe
#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT                                    0xf
#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                            0x10
#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                                      0x11
#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                                          0x12
#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                                0x13
#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK                                          0x00000010L
#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK                                   0x00000020L
#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK                                  0x00000040L
#define RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                                0x00000080L
#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                              0x00000100L
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                                 0x00000200L
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                                 0x00000400L
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                              0x00000800L
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                               0x00001000L
#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                                   0x00002000L
#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                                   0x00004000L
#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK                                      0x00008000L
#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                              0x00010000L
#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                                        0x00020000L
#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                            0x00040000L
#define RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                                  0x00080000L
//RCC_BUSNUM_CNTL1
#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT                                                                      0x0
#define RCC_BUSNUM_CNTL1__ID_MASK_MASK                                                                        0x000000FFL
//RCC_BUSNUM_LIST0
#define RCC_BUSNUM_LIST0__ID0__SHIFT                                                                          0x0
#define RCC_BUSNUM_LIST0__ID1__SHIFT                                                                          0x8
#define RCC_BUSNUM_LIST0__ID2__SHIFT                                                                          0x10
#define RCC_BUSNUM_LIST0__ID3__SHIFT                                                                          0x18
#define RCC_BUSNUM_LIST0__ID0_MASK                                                                            0x000000FFL
#define RCC_BUSNUM_LIST0__ID1_MASK                                                                            0x0000FF00L
#define RCC_BUSNUM_LIST0__ID2_MASK                                                                            0x00FF0000L
#define RCC_BUSNUM_LIST0__ID3_MASK                                                                            0xFF000000L
//RCC_BUSNUM_LIST1
#define RCC_BUSNUM_LIST1__ID4__SHIFT                                                                          0x0
#define RCC_BUSNUM_LIST1__ID5__SHIFT                                                                          0x8
#define RCC_BUSNUM_LIST1__ID6__SHIFT                                                                          0x10
#define RCC_BUSNUM_LIST1__ID7__SHIFT                                                                          0x18
#define RCC_BUSNUM_LIST1__ID4_MASK                                                                            0x000000FFL
#define RCC_BUSNUM_LIST1__ID5_MASK                                                                            0x0000FF00L
#define RCC_BUSNUM_LIST1__ID6_MASK                                                                            0x00FF0000L
#define RCC_BUSNUM_LIST1__ID7_MASK                                                                            0xFF000000L
//RCC_BUSNUM_CNTL2
#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT                                                               0x0
#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT                                                                0x8
#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT                                                                  0x10
#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT                                                      0x11
#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK                                                                 0x000000FFL
#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK                                                                  0x00000100L
#define RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK                                                                    0x00010000L
#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK                                                        0x00020000L
//RCC_CAPTURE_HOST_BUSNUM
#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT                                                              0x0
#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK                                                                0x00000001L
//RCC_HOST_BUSNUM
#define RCC_HOST_BUSNUM__HOST_ID__SHIFT                                                                       0x0
#define RCC_HOST_BUSNUM__HOST_ID_MASK                                                                         0x0000FFFFL
//RCC_PEER0_FB_OFFSET_HI
#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT                                                     0x0
#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK                                                       0x000FFFFFL
//RCC_PEER0_FB_OFFSET_LO
#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT                                                     0x0
#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT                                                            0x1f
#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK                                                       0x000FFFFFL
#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK                                                              0x80000000L
//RCC_PEER1_FB_OFFSET_HI
#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT                                                     0x0
#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK                                                       0x000FFFFFL
//RCC_PEER1_FB_OFFSET_LO
#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT                                                     0x0
#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT                                                            0x1f
#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK                                                       0x000FFFFFL
#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK                                                              0x80000000L
//RCC_PEER2_FB_OFFSET_HI
#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT                                                     0x0
#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK                                                       0x000FFFFFL
//RCC_PEER2_FB_OFFSET_LO
#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT                                                     0x0
#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT                                                            0x1f
#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK                                                       0x000FFFFFL
#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK                                                              0x80000000L
//RCC_PEER3_FB_OFFSET_HI
#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT                                                     0x0
#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK                                                       0x000FFFFFL
//RCC_PEER3_FB_OFFSET_LO
#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT                                                     0x0
#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT                                                            0x1f
#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK                                                       0x000FFFFFL
#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK                                                              0x80000000L
//RCC_CMN_LINK_CNTL
#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                                        0x0
#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                                         0x1
#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                                        0x2
#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                                     0x3
#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                                        0x10
#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                                          0x00000001L
#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                           0x00000002L
#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                                          0x00000004L
#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                                       0x00000008L
#define RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                                          0xFFFF0000L
//RCC_EP_REQUESTERID_RESTORE
#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                                       0x0
#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                                       0x8
#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                                         0x000000FFL
#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                                         0x00001F00L
//RCC_LTR_LSWITCH_CNTL
#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                                    0x0
#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                                      0x000003FFL
//RCC_MH_ARB_CNTL
#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                                   0x0
#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                           0x1
#define RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                                     0x00000001L
#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                             0x00007FFEL


// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975]
//BIF_MM_INDACCESS_CNTL
#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                        0x1
#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                          0x00000002L
//BUS_CNTL
#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT                                                                       0x3
#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT                                                                       0x4
#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT                                                                     0x5
#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                                0x6
#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                                0x7
#define BUS_CNTL__SET_AZ_TC__SHIFT                                                                            0xa
#define BUS_CNTL__SET_MC_TC__SHIFT                                                                            0xd
#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                        0x10
#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                        0x11
#define BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                                       0x12
#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT                                                        0x13
#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT                                                        0x14
#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT                                                      0x15
#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT                                                           0x16
#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT                                                           0x17
#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT                                                                  0x18
#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                                  0x19
#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT                                                          0x1b
#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT                                                          0x1c
#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                             0x1d
#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                                  0x1e
#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                                  0x1f
#define BUS_CNTL__PMI_INT_DIS_EP_MASK                                                                         0x00000008L
#define BUS_CNTL__PMI_INT_DIS_DN_MASK                                                                         0x00000010L
#define BUS_CNTL__PMI_INT_DIS_SWUS_MASK                                                                       0x00000020L
#define BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                                  0x00000040L
#define BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                                  0x00000080L
#define BUS_CNTL__SET_AZ_TC_MASK                                                                              0x00001C00L
#define BUS_CNTL__SET_MC_TC_MASK                                                                              0x0000E000L
#define BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                          0x00010000L
#define BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                          0x00020000L
#define BUS_CNTL__RD_STALL_IO_WR_MASK                                                                         0x00040000L
#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK                                                          0x00080000L
#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK                                                          0x00100000L
#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK                                                        0x00200000L
#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK                                                             0x00400000L
#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK                                                             0x00800000L
#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK                                                                    0x01000000L
#define BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                                    0x02000000L
#define BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK                                                            0x08000000L
#define BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK                                                            0x10000000L
#define BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                               0x20000000L
#define BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                                    0x40000000L
#define BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                                    0x80000000L
//BIF_SCRATCH0
#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                                     0x0
#define BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                                       0xFFFFFFFFL
//BIF_SCRATCH1
#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                                     0x0
#define BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                                       0xFFFFFFFFL
//BX_RESET_EN
#define BX_RESET_EN__COR_RESET_EN__SHIFT                                                                      0x0
#define BX_RESET_EN__REG_RESET_EN__SHIFT                                                                      0x1
#define BX_RESET_EN__STY_RESET_EN__SHIFT                                                                      0x2
#define BX_RESET_EN__FLR_TWICE_EN__SHIFT                                                                      0x8
#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                          0x10
#define BX_RESET_EN__COR_RESET_EN_MASK                                                                        0x00000001L
#define BX_RESET_EN__REG_RESET_EN_MASK                                                                        0x00000002L
#define BX_RESET_EN__STY_RESET_EN_MASK                                                                        0x00000004L
#define BX_RESET_EN__FLR_TWICE_EN_MASK                                                                        0x00000100L
#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                            0x00010000L
//MM_CFGREGS_CNTL
#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                               0x0
#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                                0x6
#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                               0x1f
#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                                 0x00000007L
#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                                  0x000000C0L
#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                                 0x80000000L
//BX_RESET_CNTL
#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                                   0x0
#define BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                                     0x00000001L
//INTERRUPT_CNTL
#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                           0x0
#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                                 0x1
#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                             0x3
#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                               0x4
#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                                  0x8
#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                         0xf
#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                                       0x10
#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                           0x11
#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                             0x00000001L
#define INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                                   0x00000002L
#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                               0x00000008L
#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                                 0x000000F0L
#define INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                                    0x00000100L
#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                           0x00008000L
#define INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                         0x00010000L
#define INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                             0x00020000L
//INTERRUPT_CNTL2
#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                              0x0
#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                                0xFFFFFFFFL
//CLKREQB_PAD_CNTL
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                                0x0
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                              0x1
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                             0x2
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                            0x3
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                              0x5
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                              0x6
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                              0x7
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                              0x8
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                            0x9
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                             0xa
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                           0xb
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                          0xc
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                                0xd
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                                  0x00000001L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                                0x00000002L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                               0x00000004L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                              0x00000018L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                                0x00000020L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                                0x00000040L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                                0x00000080L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                                0x00000100L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                              0x00000200L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                               0x00000400L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                             0x00000800L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                            0x00001000L
#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                                  0x00002000L
//BIF_FEATURES_CONTROL_MISC
#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                                  0x0
#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                                  0x1
#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                                  0x2
#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                                  0x3
#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                              0xc
#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                                  0xd
#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                                   0xf
#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT                                                0x11
#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT                                                0x12
#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                           0x18
#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                                    0x00000001L
#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                                    0x00000002L
#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                                    0x00000004L
#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                                    0x00000008L
#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                                0x00001000L
#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                                    0x00002000L
#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                                     0x00008000L
#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK                                                  0x00020000L
#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK                                                  0x00040000L
#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                             0x01000000L
//BIF_DOORBELL_CNTL
#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                               0x0
#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                             0x1
#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                            0x2
#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                                 0x3
#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                         0x4
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                          0x18
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                                       0x19
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                                       0x1a
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                                       0x1b
#define BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                                 0x00000001L
#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                               0x00000002L
#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                              0x00000004L
#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                                   0x00000008L
#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                           0x00000010L
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                            0x01000000L
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                         0x02000000L
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                         0x04000000L
#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                         0x08000000L
//BIF_DOORBELL_INT_CNTL
#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                               0x0
#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT                                               0x1
#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                                0x10
#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT                                                0x11
#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                                 0x00000001L
#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK                                                 0x00000002L
#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                                  0x00010000L
#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK                                                  0x00020000L
//BIF_FB_EN
#define BIF_FB_EN__FB_READ_EN__SHIFT                                                                          0x0
#define BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                         0x1
#define BIF_FB_EN__FB_READ_EN_MASK                                                                            0x00000001L
#define BIF_FB_EN__FB_WRITE_EN_MASK                                                                           0x00000002L
//BIF_BUSY_DELAY_CNTR
#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT                                                                 0x0
#define BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK                                                                   0x0000003FL
//BIF_MST_TRANS_PENDING_VF
#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                                0x0
#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                                  0x0000FFFFL
//BIF_SLV_TRANS_PENDING_VF
#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                                0x0
#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                                  0x0000FFFFL
//BACO_CNTL
#define BACO_CNTL__BACO_EN__SHIFT                                                                             0x0
#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT                                                                0x1
#define BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                                       0x2
#define BACO_CNTL__BACO_POWER_OFF__SHIFT                                                                      0x3
#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                                  0x5
#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                                  0x6
#define BACO_CNTL__BACO_MODE__SHIFT                                                                           0x8
#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                                 0x9
#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                                      0x1f
#define BACO_CNTL__BACO_EN_MASK                                                                               0x00000001L
#define BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK                                                                  0x00000002L
#define BACO_CNTL__BACO_DUMMY_EN_MASK                                                                         0x00000004L
#define BACO_CNTL__BACO_POWER_OFF_MASK                                                                        0x00000008L
#define BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                                    0x00000020L
#define BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                                    0x00000040L
#define BACO_CNTL__BACO_MODE_MASK                                                                             0x00000100L
#define BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                                   0x00000200L
#define BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                        0x80000000L
//BIF_BACO_EXIT_TIME0
#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                                  0x0
#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                                    0x000FFFFFL
//BIF_BACO_EXIT_TIMER1
#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                                 0x0
#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                                    0x18
#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT                                0x19
#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                         0x1a
#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                                   0x1b
#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                                    0x1c
#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                            0x1d
#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                             0x1f
#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                                   0x000FFFFFL
#define BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                                      0x01000000L
#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK                                  0x02000000L
#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                           0x04000000L
#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                                     0x08000000L
#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                                      0x10000000L
#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                              0x60000000L
#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                               0x80000000L
//BIF_BACO_EXIT_TIMER2
#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                                 0x0
#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                                   0x000FFFFFL
//BIF_BACO_EXIT_TIMER3
#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                             0x0
#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                               0x000FFFFFL
//BIF_BACO_EXIT_TIMER4
#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                              0x0
#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                                0x000FFFFFL
//MEM_TYPE_CNTL
#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                                0x0
#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                                  0x00000001L
//SMU_BIF_VDDGFX_PWR_STATUS
#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT                                                  0x0
#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK                                                    0x00000001L
//BIF_VDDGFX_GFX0_LOWER
#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_GFX0_UPPER
#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_GFX1_LOWER
#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_GFX1_UPPER
#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_GFX2_LOWER
#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_GFX2_UPPER
#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_GFX3_LOWER
#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_GFX3_UPPER
#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_GFX4_LOWER
#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_GFX4_UPPER
#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_GFX5_LOWER
#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_GFX5_UPPER
#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_RSV1_LOWER
#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_RSV1_UPPER
#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_RSV2_LOWER
#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_RSV2_UPPER
#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_RSV3_LOWER
#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_RSV3_UPPER
#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_RSV4_LOWER
#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT                                                  0x1e
#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT                                                0x1f
#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK                                                     0x0003FFFCL
#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK                                                    0x40000000L
#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK                                                  0x80000000L
//BIF_VDDGFX_RSV4_UPPER
#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT                                                   0x2
#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK                                                     0x0003FFFCL
//BIF_VDDGFX_FB_CMP
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT                                                        0x0
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT                                                      0x1
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT                                                       0x2
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT                                                     0x3
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT                                                        0x4
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT                                                      0x5
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK                                                          0x00000001L
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK                                                        0x00000002L
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK                                                         0x00000004L
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK                                                       0x00000008L
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK                                                          0x00000010L
#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK                                                        0x00000020L
//BIF_DOORBELL_GBLAPER1_LOWER
#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT                                           0x2
#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT                                              0x1f
#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK                                             0x00000FFCL
#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK                                                0x80000000L
//BIF_DOORBELL_GBLAPER1_UPPER
#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT                                           0x2
#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK                                             0x00000FFCL
//BIF_DOORBELL_GBLAPER2_LOWER
#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT                                           0x2
#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT                                              0x1f
#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK                                             0x00000FFCL
#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK                                                0x80000000L
//BIF_DOORBELL_GBLAPER2_UPPER
#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT                                           0x2
#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK                                             0x00000FFCL
//REMAP_HDP_MEM_FLUSH_CNTL
#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                              0x2
#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                                0x0007FFFCL
//REMAP_HDP_REG_FLUSH_CNTL
#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                              0x2
#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                                0x0007FFFCL
//BIF_RB_CNTL
#define BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                         0x0
#define BIF_RB_CNTL__RB_SIZE__SHIFT                                                                           0x1
#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                             0x8
#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                              0x9
#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                                       0x11
#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                               0x1f
#define BIF_RB_CNTL__RB_ENABLE_MASK                                                                           0x00000001L
#define BIF_RB_CNTL__RB_SIZE_MASK                                                                             0x0000003EL
#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                               0x00000100L
#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                                0x00003E00L
#define BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                         0x00020000L
#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                                 0x80000000L
//BIF_RB_BASE
#define BIF_RB_BASE__ADDR__SHIFT                                                                              0x0
#define BIF_RB_BASE__ADDR_MASK                                                                                0xFFFFFFFFL
//BIF_RB_RPTR
#define BIF_RB_RPTR__OFFSET__SHIFT                                                                            0x2
#define BIF_RB_RPTR__OFFSET_MASK                                                                              0x0003FFFCL
//BIF_RB_WPTR
#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                                   0x0
#define BIF_RB_WPTR__OFFSET__SHIFT                                                                            0x2
#define BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                                     0x00000001L
#define BIF_RB_WPTR__OFFSET_MASK                                                                              0x0003FFFCL
//BIF_RB_WPTR_ADDR_HI
#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                                      0x0
#define BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                        0x000000FFL
//BIF_RB_WPTR_ADDR_LO
#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                                      0x2
#define BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                        0xFFFFFFFCL
//MAILBOX_INDEX
#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                                   0x0
#define MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                                     0x0000001FL
//BIF_UVD_GPUIOV_CFG_SIZE
#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT                                                   0x0
#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK                                                     0x0000000FL
//BIF_VCE_GPUIOV_CFG_SIZE
#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT                                                   0x0
#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK                                                     0x0000000FL
//BIF_GFX_SDMA_GPUIOV_CFG_SIZE
#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                                         0x0
#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                           0x0000000FL
//BIF_PERSTB_PAD_CNTL
#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                           0x0
#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                             0x0000FFFFL
//BIF_PX_EN_PAD_CNTL
#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                             0x0
#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                               0x000000FFL
//BIF_REFPADKIN_PAD_CNTL
#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                                     0x0
#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                                       0x000000FFL
//BIF_CLKREQB_PAD_CNTL
#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                         0x0
#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                           0x00FFFFFFL


// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
//BIF_BX_PF0_BIF_BME_STATUS
#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
//BIF_BX_PF0_BIF_TRANS_PENDING
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF0_MAILBOX_CONTROL
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
//BIF_BX_PF0_MAILBOX_INT_CNTL
#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
//BIF_BX_PF0_BIF_VMHV_MAILBOX
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L


// addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487]
//NGDC_SDP_PORT_CTRL
#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                      0x0
#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK                                                        0x0000003FL
//SHUB_REGS_IF_CTL
#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                     0x0
#define SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                       0x00000001L
//NGDC_RESERVED_0
#define NGDC_RESERVED_0__RESERVED__SHIFT                                                                      0x0
#define NGDC_RESERVED_0__RESERVED_MASK                                                                        0xFFFFFFFFL
//NGDC_RESERVED_1
#define NGDC_RESERVED_1__RESERVED__SHIFT                                                                      0x0
#define NGDC_RESERVED_1__RESERVED_MASK                                                                        0xFFFFFFFFL
//NGDC_SDP_PORT_CTRL_SOCCLK
#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT                                        0x0
#define NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK                                          0x0000003FL
//BIF_SDMA0_DOORBELL_RANGE
#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                               0x2
#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                                 0x10
#define BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                                 0x00000FFCL
#define BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                                   0x001F0000L
//BIF_SDMA1_DOORBELL_RANGE
#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT                                                               0x2
#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT                                                                 0x10
#define BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK                                                                 0x00000FFCL
#define BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK                                                                   0x001F0000L
//BIF_IH_DOORBELL_RANGE
#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                                  0x2
#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                                    0x10
#define BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                                    0x00000FFCL
#define BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                      0x001F0000L
//BIF_MMSCH0_DOORBELL_RANGE
#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT                                                              0x2
#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT                                                                0x10
#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK                                                                0x00000FFCL
#define BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK                                                                  0x001F0000L
//BIF_DOORBELL_FENCE_CNTL
#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT                                                 0x0
#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK                                                   0x00000001L
//S2A_MISC_CNTL
#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT                                                0x0
#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT                                                0x1
#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT                                                   0x2
#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT                                                              0x3
#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK                                                  0x00000001L
#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK                                                  0x00000002L
#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK                                                     0x00000004L
#define S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK                                                                0x00000008L


// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2
//RCC_PF_0_GFXMSIX_VECT0_ADDR_LO
#define RCC_PF_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                                    0x2
#define RCC_PF_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                                      0xFFFFFFFCL
//RCC_PF_0_GFXMSIX_VECT0_ADDR_HI
#define RCC_PF_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                                    0x0
#define RCC_PF_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                                      0xFFFFFFFFL
//RCC_PF_0_GFXMSIX_VECT0_MSG_DATA
#define RCC_PF_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                                      0x0
#define RCC_PF_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                                        0xFFFFFFFFL
//RCC_PF_0_GFXMSIX_VECT0_CONTROL
#define RCC_PF_0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                                       0x0
#define RCC_PF_0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                         0x00000001L
//RCC_PF_0_GFXMSIX_VECT1_ADDR_LO
#define RCC_PF_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                                    0x2
#define RCC_PF_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                                      0xFFFFFFFCL
//RCC_PF_0_GFXMSIX_VECT1_ADDR_HI
#define RCC_PF_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                                    0x0
#define RCC_PF_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                                      0xFFFFFFFFL
//RCC_PF_0_GFXMSIX_VECT1_MSG_DATA
#define RCC_PF_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                                      0x0
#define RCC_PF_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                                        0xFFFFFFFFL
//RCC_PF_0_GFXMSIX_VECT1_CONTROL
#define RCC_PF_0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                                       0x0
#define RCC_PF_0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                         0x00000001L
//RCC_PF_0_GFXMSIX_VECT2_ADDR_LO
#define RCC_PF_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                                    0x2
#define RCC_PF_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                                      0xFFFFFFFCL
//RCC_PF_0_GFXMSIX_VECT2_ADDR_HI
#define RCC_PF_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                                    0x0
#define RCC_PF_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                                      0xFFFFFFFFL
//RCC_PF_0_GFXMSIX_VECT2_MSG_DATA
#define RCC_PF_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                                      0x0
#define RCC_PF_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                                        0xFFFFFFFFL
//RCC_PF_0_GFXMSIX_VECT2_CONTROL
#define RCC_PF_0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                                       0x0
#define RCC_PF_0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                         0x00000001L
//RCC_PF_0_GFXMSIX_PBA
#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                                      0x0
#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                                      0x1
#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT                                                      0x2
#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                                        0x00000001L
#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                                        0x00000002L
#define RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK                                                        0x00000004L


// addressBlock: nbio_nbif_gdc_GDCDEC
//GDC1_NGDC_SDP_PORT_CTRL
#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                 0x0
#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK                                                   0x0000003FL
//GDC1_SHUB_REGS_IF_CTL
#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                0x0
#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                  0x00000001L
//GDC1_NGDC_RESERVED_0
#define GDC1_NGDC_RESERVED_0__RESERVED__SHIFT                                                                 0x0
#define GDC1_NGDC_RESERVED_0__RESERVED_MASK                                                                   0xFFFFFFFFL
//GDC1_NGDC_RESERVED_1
#define GDC1_NGDC_RESERVED_1__RESERVED__SHIFT                                                                 0x0
#define GDC1_NGDC_RESERVED_1__RESERVED_MASK                                                                   0xFFFFFFFFL
//GDC1_NGDC_SDP_PORT_CTRL_SOCCLK
#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK__SHIFT                                   0x0
#define GDC1_NGDC_SDP_PORT_CTRL_SOCCLK__SDP_DISCON_HYSTERESIS_SOCCLK_MASK                                     0x0000003FL
//GDC1_BIF_SDMA0_DOORBELL_RANGE
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA0_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_SDMA1_DOORBELL_RANGE
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT                                                          0x2
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT                                                            0x10
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__OFFSET_MASK                                                            0x00000FFCL
#define GDC1_BIF_SDMA1_DOORBELL_RANGE__SIZE_MASK                                                              0x001F0000L
//GDC1_BIF_IH_DOORBELL_RANGE
#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT                                                             0x2
#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE__SHIFT                                                               0x10
#define GDC1_BIF_IH_DOORBELL_RANGE__OFFSET_MASK                                                               0x00000FFCL
#define GDC1_BIF_IH_DOORBELL_RANGE__SIZE_MASK                                                                 0x001F0000L
//GDC1_BIF_MMSCH0_DOORBELL_RANGE
#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT                                                         0x2
#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT                                                           0x10
#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__OFFSET_MASK                                                           0x00000FFCL
#define GDC1_BIF_MMSCH0_DOORBELL_RANGE__SIZE_MASK                                                             0x001F0000L
//GDC1_BIF_DOORBELL_FENCE_CNTL
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT                                            0x0
#define GDC1_BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE_MASK                                              0x00000001L
//GDC1_S2A_MISC_CNTL
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT                                           0x0
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT                                           0x1
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT                                              0x2
#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT                                                         0x3
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS_MASK                                             0x00000001L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS_MASK                                             0x00000002L
#define GDC1_S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS_MASK                                                0x00000004L
#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK                                                           0x00000008L


// addressBlock: nbio_nbif_syshub_mmreg_direct_syshubdirect
//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x2
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x3
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x4
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x5
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x6
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x7
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x11
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x12
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x13
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x14
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x15
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x16
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT               0x17
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x1c
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT                                 0x1f
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000004L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000008L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000010L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000020L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000040L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00000080L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00010000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00020000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00040000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00080000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00100000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00200000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00400000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                 0x00800000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x10000000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK                                   0x80000000L
//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT                             0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK                               0x0000FFFFL
//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT  0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT  0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT  0xf
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT  0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT  0x11
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK  0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK  0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK  0x00008000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK  0x00010000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK  0x00020000L
//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT   0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT   0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT   0xf
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT   0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT   0x11
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK     0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK     0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK     0x00008000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK     0x00010000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK     0x00020000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                0x5
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                  0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                  0x0000001EL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                  0x000001E0L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                0x5
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                  0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                  0x0000001EL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                  0x000001E0L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
//SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL
#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT                                               0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT                                       0x8
#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK                                                 0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK                                         0x0000FF00L
#define SYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK                                       0x00FF0000L
//SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT                                   0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT                                   0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT                                   0x2
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT                                   0x3
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT                                   0x4
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT                                   0x5
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT                                   0x6
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT                                   0x7
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT                                   0x8
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT                                   0x9
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT                                  0xa
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT                                  0xb
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT                                  0xc
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT                                  0xd
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT                                  0xe
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT                                  0xf
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT                                    0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK                                     0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK                                     0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK                                     0x00000004L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK                                     0x00000008L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK                                     0x00000010L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK                                     0x00000020L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK                                     0x00000040L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK                                     0x00000080L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK                                     0x00000100L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK                                     0x00000200L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK                                    0x00000400L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK                                    0x00000800L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK                                    0x00001000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK                                    0x00002000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK                                    0x00004000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK                                    0x00008000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK                                      0x00010000L
//SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER
#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT                                           0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK                                             0xFFFFFFFFL
//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT                             0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT                           0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT                     0x2
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT                        0xa
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT                        0xb
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT                       0xc
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT                        0xd
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK                               0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK                             0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK                       0x000003FCL
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK                          0x00000400L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK                          0x00000800L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK                         0x00001000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK                          0x00002000L
//SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH
#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH__SHIFT                                                    0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH__SCRATCH_MASK                                                      0xFFFFFFFFL
//SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK
#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT                                           0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT                                               0x2
#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK                                             0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK                                                 0x00000004L
//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x2
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x3
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x4
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x5
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x6
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x7
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x11
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x12
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x13
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x14
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x15
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x16
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT             0x17
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT              0x1c
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT                               0x1f
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000004L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000008L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000010L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000020L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000040L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00000080L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00010000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00020000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00040000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00080000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00100000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00200000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00400000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK               0x00800000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                0x10000000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK                                 0x80000000L
//SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT                           0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK                             0x0000FFFFL
//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT  0xf
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT  0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK  0x00008000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK  0x00010000L
//SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT  0xf
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT  0x10
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK   0x00008000L
#define SYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK   0x00010000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                0x5
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                  0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                  0x0000001EL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                  0x000001E0L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                0x5
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                  0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                  0x0000001EL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                  0x000001E0L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                0x1
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                              0x8
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                           0x9
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT                                     0x10
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT                                    0x18
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                  0x00000002L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                0x00000100L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                             0x00001E00L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK                                       0x00FF0000L
#define SYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK                                      0xFF000000L
//SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT                           0x0
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT                         0x1
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT                   0x2
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT                      0xa
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT                      0xb
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT                     0xc
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK                             0x00000001L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK                           0x00000002L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK                     0x000003FCL
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK                        0x00000400L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK                        0x00000800L
#define SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK                       0x00001000L
//SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT                           0x0
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT                          0x1
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK                             0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK                            0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT                           0x0
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT                          0x1
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK                             0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK                            0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT                           0x0
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT                          0x1
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK                             0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK                            0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT                                  0x0
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT                                 0x1
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK                                    0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK                                   0x00000002L
//SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS
#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT                           0x0
#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT                          0x1
#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK                             0x00000001L
#define SYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK                            0x00000002L


// addressBlock: nbio_nbif_nbif_sion_SIONDEC
//SION_CL0_RdRsp_BurstTarget_REG0
#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL0_RdRsp_BurstTarget_REG1
#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL0_RdRsp_TimeSlot_REG0
#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL0_RdRsp_TimeSlot_REG1
#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL0_WrRsp_BurstTarget_REG0
#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL0_WrRsp_BurstTarget_REG1
#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL0_WrRsp_TimeSlot_REG0
#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL0_WrRsp_TimeSlot_REG1
#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL0_Req_BurstTarget_REG0
#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL0_Req_BurstTarget_REG1
#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL0_Req_TimeSlot_REG0
#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL0_Req_TimeSlot_REG1
#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL0_ReqPoolCredit_Alloc_REG0
#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL0_ReqPoolCredit_Alloc_REG1
#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL0_DataPoolCredit_Alloc_REG0
#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL0_DataPoolCredit_Alloc_REG1
#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL0_RdRspPoolCredit_Alloc_REG0
#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL0_RdRspPoolCredit_Alloc_REG1
#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL0_WrRspPoolCredit_Alloc_REG0
#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL0_WrRspPoolCredit_Alloc_REG1
#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL1_RdRsp_BurstTarget_REG0
#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL1_RdRsp_BurstTarget_REG1
#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL1_RdRsp_TimeSlot_REG0
#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL1_RdRsp_TimeSlot_REG1
#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL1_WrRsp_BurstTarget_REG0
#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL1_WrRsp_BurstTarget_REG1
#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL1_WrRsp_TimeSlot_REG0
#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL1_WrRsp_TimeSlot_REG1
#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL1_Req_BurstTarget_REG0
#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL1_Req_BurstTarget_REG1
#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL1_Req_TimeSlot_REG0
#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL1_Req_TimeSlot_REG1
#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL1_ReqPoolCredit_Alloc_REG0
#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL1_ReqPoolCredit_Alloc_REG1
#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL1_DataPoolCredit_Alloc_REG0
#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL1_DataPoolCredit_Alloc_REG1
#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL1_RdRspPoolCredit_Alloc_REG0
#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL1_RdRspPoolCredit_Alloc_REG1
#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL1_WrRspPoolCredit_Alloc_REG0
#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL1_WrRspPoolCredit_Alloc_REG1
#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL2_RdRsp_BurstTarget_REG0
#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL2_RdRsp_BurstTarget_REG1
#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL2_RdRsp_TimeSlot_REG0
#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL2_RdRsp_TimeSlot_REG1
#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL2_WrRsp_BurstTarget_REG0
#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL2_WrRsp_BurstTarget_REG1
#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL2_WrRsp_TimeSlot_REG0
#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL2_WrRsp_TimeSlot_REG1
#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL2_Req_BurstTarget_REG0
#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL2_Req_BurstTarget_REG1
#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL2_Req_TimeSlot_REG0
#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL2_Req_TimeSlot_REG1
#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL2_ReqPoolCredit_Alloc_REG0
#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL2_ReqPoolCredit_Alloc_REG1
#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL2_DataPoolCredit_Alloc_REG0
#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL2_DataPoolCredit_Alloc_REG1
#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL2_RdRspPoolCredit_Alloc_REG0
#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL2_RdRspPoolCredit_Alloc_REG1
#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL2_WrRspPoolCredit_Alloc_REG0
#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL2_WrRspPoolCredit_Alloc_REG1
#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL3_RdRsp_BurstTarget_REG0
#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL3_RdRsp_BurstTarget_REG1
#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL3_RdRsp_TimeSlot_REG0
#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL3_RdRsp_TimeSlot_REG1
#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL3_WrRsp_BurstTarget_REG0
#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL3_WrRsp_BurstTarget_REG1
#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL3_WrRsp_TimeSlot_REG0
#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL3_WrRsp_TimeSlot_REG1
#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL3_Req_BurstTarget_REG0
#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL3_Req_BurstTarget_REG1
#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL3_Req_TimeSlot_REG0
#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL3_Req_TimeSlot_REG1
#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL3_ReqPoolCredit_Alloc_REG0
#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL3_ReqPoolCredit_Alloc_REG1
#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL3_DataPoolCredit_Alloc_REG0
#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL3_DataPoolCredit_Alloc_REG1
#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL3_RdRspPoolCredit_Alloc_REG0
#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL3_RdRspPoolCredit_Alloc_REG1
#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL3_WrRspPoolCredit_Alloc_REG0
#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL3_WrRspPoolCredit_Alloc_REG1
#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL4_RdRsp_BurstTarget_REG0
#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL4_RdRsp_BurstTarget_REG1
#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL4_RdRsp_TimeSlot_REG0
#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL4_RdRsp_TimeSlot_REG1
#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL4_WrRsp_BurstTarget_REG0
#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL4_WrRsp_BurstTarget_REG1
#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL4_WrRsp_TimeSlot_REG0
#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL4_WrRsp_TimeSlot_REG1
#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL4_Req_BurstTarget_REG0
#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL4_Req_BurstTarget_REG1
#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL4_Req_TimeSlot_REG0
#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL4_Req_TimeSlot_REG1
#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL4_ReqPoolCredit_Alloc_REG0
#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL4_ReqPoolCredit_Alloc_REG1
#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL4_DataPoolCredit_Alloc_REG0
#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL4_DataPoolCredit_Alloc_REG1
#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL4_RdRspPoolCredit_Alloc_REG0
#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL4_RdRspPoolCredit_Alloc_REG1
#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL4_WrRspPoolCredit_Alloc_REG0
#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL4_WrRspPoolCredit_Alloc_REG1
#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL5_RdRsp_BurstTarget_REG0
#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL5_RdRsp_BurstTarget_REG1
#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL5_RdRsp_TimeSlot_REG0
#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL5_RdRsp_TimeSlot_REG1
#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL5_WrRsp_BurstTarget_REG0
#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                        0x0
#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                          0xFFFFFFFFL
//SION_CL5_WrRsp_BurstTarget_REG1
#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                                       0x0
#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                         0xFFFFFFFFL
//SION_CL5_WrRsp_TimeSlot_REG0
#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                              0x0
#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                                0xFFFFFFFFL
//SION_CL5_WrRsp_TimeSlot_REG1
#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                             0x0
#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                               0xFFFFFFFFL
//SION_CL5_Req_BurstTarget_REG0
#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                            0x0
#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                              0xFFFFFFFFL
//SION_CL5_Req_BurstTarget_REG1
#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                           0x0
#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                             0xFFFFFFFFL
//SION_CL5_Req_TimeSlot_REG0
#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                                  0x0
#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                                    0xFFFFFFFFL
//SION_CL5_Req_TimeSlot_REG1
#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                                 0x0
#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                                   0xFFFFFFFFL
//SION_CL5_ReqPoolCredit_Alloc_REG0
#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                                    0x0
#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                                      0xFFFFFFFFL
//SION_CL5_ReqPoolCredit_Alloc_REG1
#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                                   0x0
#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                                     0xFFFFFFFFL
//SION_CL5_DataPoolCredit_Alloc_REG0
#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                                  0x0
#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                                    0xFFFFFFFFL
//SION_CL5_DataPoolCredit_Alloc_REG1
#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                                 0x0
#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                                   0xFFFFFFFFL
//SION_CL5_RdRspPoolCredit_Alloc_REG0
#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL5_RdRspPoolCredit_Alloc_REG1
#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CL5_WrRspPoolCredit_Alloc_REG0
#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                                0x0
#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                                  0xFFFFFFFFL
//SION_CL5_WrRspPoolCredit_Alloc_REG1
#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                               0x0
#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                                 0xFFFFFFFFL
//SION_CNTL_REG0
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT                                0x0
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT                                0x1
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT                                0x2
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT                                0x3
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT                                0x4
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT                                0x5
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT                                0x6
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT                                0x7
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT                                0x8
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT                                0x9
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT                                0xa
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT                                0xb
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT                                0xc
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT                                0xd
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT                                0xe
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT                                0xf
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT                                0x10
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT                                0x11
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT                                0x12
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT                                0x13
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK                                  0x00000001L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK                                  0x00000002L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK                                  0x00000004L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK                                  0x00000008L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK                                  0x00000010L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK                                  0x00000020L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK                                  0x00000040L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK                                  0x00000080L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK                                  0x00000100L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK                                  0x00000200L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK                                  0x00000400L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK                                  0x00000800L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK                                  0x00001000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK                                  0x00002000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK                                  0x00004000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK                                  0x00008000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK                                  0x00010000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK                                  0x00020000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK                                  0x00040000L
#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK                                  0x00080000L
//SION_CNTL_REG1
#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT                                                    0x0
#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT                                                              0x8
#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD_MASK                                                      0x000000FFL
#define SION_CNTL_REG1__CG_OFF_HYSTERESIS_MASK                                                                0x0000FF00L


// addressBlock: nbio_nbif_gdc_rst_GDCRST_DEC
//SHUB_PF_FLR_RST
#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                              0x0
#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                              0x1
#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT                                                              0x2
#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT                                                              0x3
#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT                                                              0x4
#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT                                                              0x5
#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT                                                              0x6
#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT                                                              0x7
#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                0x00000001L
#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                0x00000002L
#define SHUB_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK                                                                0x00000004L
#define SHUB_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK                                                                0x00000008L
#define SHUB_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK                                                                0x00000010L
#define SHUB_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK                                                                0x00000020L
#define SHUB_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK                                                                0x00000040L
#define SHUB_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK                                                                0x00000080L
//SHUB_GFX_DRV_VPU_RST
#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT                                                        0x0
#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK                                                          0x00000001L
//SHUB_LINK_RESET
#define SHUB_LINK_RESET__LINK_RESET__SHIFT                                                                    0x0
#define SHUB_LINK_RESET__LINK_RESET_MASK                                                                      0x00000001L
//SHUB_PF0_VF_FLR_RST
#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT                                                           0x0
#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT                                                           0x1
#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT                                                           0x2
#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT                                                           0x3
#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT                                                           0x4
#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT                                                           0x5
#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT                                                           0x6
#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT                                                           0x7
#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT                                                           0x8
#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT                                                           0x9
#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT                                                          0xa
#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT                                                          0xb
#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT                                                          0xc
#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT                                                          0xd
#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT                                                          0xe
#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT                                                          0xf
#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT                                                        0x1f
#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK                                                             0x00000001L
#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK                                                             0x00000002L
#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK                                                             0x00000004L
#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK                                                             0x00000008L
#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK                                                             0x00000010L
#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK                                                             0x00000020L
#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK                                                             0x00000040L
#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK                                                             0x00000080L
#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK                                                             0x00000100L
#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK                                                             0x00000200L
#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK                                                            0x00000400L
#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK                                                            0x00000800L
#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK                                                            0x00001000L
#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK                                                            0x00002000L
#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK                                                            0x00004000L
#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK                                                            0x00008000L
#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK                                                          0x80000000L
//SHUB_HARD_RST_CTRL
#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT                                                               0x0
#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT                                                               0x1
#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT                                                               0x2
#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT                                                            0x3
#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                          0x4
#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK                                                                 0x00000001L
#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK                                                                 0x00000002L
#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK                                                                 0x00000004L
#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK                                                              0x00000008L
#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                            0x00000010L
//SHUB_SOFT_RST_CTRL
#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT                                                               0x0
#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT                                                               0x1
#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT                                                               0x2
#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT                                                            0x3
#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                          0x4
#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK                                                                 0x00000001L
#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK                                                                 0x00000002L
#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK                                                                 0x00000004L
#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK                                                              0x00000008L
#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                            0x00000010L
//SHUB_SDP_PORT_RST
#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT                                                                0x0
#define SHUB_SDP_PORT_RST__SDP_PORT_RST_MASK                                                                  0x00000001L
//SHUB_RST_MISC_TRL
#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC__SHIFT                                                        0x0
#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE__SHIFT                                                         0x10
#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_ATOMIC_MASK                                                          0x00000001L
#define SHUB_RST_MISC_TRL__RSMU_SOFT_RST_CYCLE_MASK                                                           0x00FF0000L


// addressBlock: nbio_nbif_gdc_ras_gdc_ras_regblk
//GDC_RAS_LEAF0_CTRL
#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//GDC_RAS_LEAF1_CTRL
#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//GDC_RAS_LEAF2_CTRL
#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//GDC_RAS_LEAF3_CTRL
#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//GDC_RAS_LEAF4_CTRL
#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//GDC_RAS_LEAF5_CTRL
#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L


// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
//BIF_CFG_DEV0_SWDS1_VENDOR_ID
#define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_VENDOR_ID__VENDOR_ID_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_SWDS1_DEVICE_ID
#define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_ID__DEVICE_ID_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_SWDS1_COMMAND
#define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN__SHIFT                                                            0x0
#define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN__SHIFT                                                           0x1
#define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN__SHIFT                                                      0x2
#define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                   0x3
#define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN__SHIFT                                                       0x5
#define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                              0x6
#define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING__SHIFT                                                        0x7
#define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN__SHIFT                                                            0x8
#define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN__SHIFT                                                        0x9
#define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS__SHIFT                                                            0xa
#define BIF_CFG_DEV0_SWDS1_COMMAND__IOEN_DN_MASK                                                              0x0001L
#define BIF_CFG_DEV0_SWDS1_COMMAND__MEMEN_DN_MASK                                                             0x0002L
#define BIF_CFG_DEV0_SWDS1_COMMAND__BUS_MASTER_EN_MASK                                                        0x0004L
#define BIF_CFG_DEV0_SWDS1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                     0x0008L
#define BIF_CFG_DEV0_SWDS1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_SWDS1_COMMAND__PAL_SNOOP_EN_MASK                                                         0x0020L
#define BIF_CFG_DEV0_SWDS1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                0x0040L
#define BIF_CFG_DEV0_SWDS1_COMMAND__AD_STEPPING_MASK                                                          0x0080L
#define BIF_CFG_DEV0_SWDS1_COMMAND__SERR_EN_MASK                                                              0x0100L
#define BIF_CFG_DEV0_SWDS1_COMMAND__FAST_B2B_EN_MASK                                                          0x0200L
#define BIF_CFG_DEV0_SWDS1_COMMAND__INT_DIS_MASK                                                              0x0400L
//BIF_CFG_DEV0_SWDS1_STATUS
#define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS__SHIFT                                                          0x3
#define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST__SHIFT                                                            0x4
#define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_EN__SHIFT                                                           0x5
#define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                            0x8
#define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING__SHIFT                                                       0x9
#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                 0xb
#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                               0xc
#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                               0xd
#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                               0xe
#define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                               0xf
#define BIF_CFG_DEV0_SWDS1_STATUS__INT_STATUS_MASK                                                            0x0008L
#define BIF_CFG_DEV0_SWDS1_STATUS__CAP_LIST_MASK                                                              0x0010L
#define BIF_CFG_DEV0_SWDS1_STATUS__PCI_66_EN_MASK                                                             0x0020L
#define BIF_CFG_DEV0_SWDS1_STATUS__FAST_BACK_CAPABLE_MASK                                                     0x0080L
#define BIF_CFG_DEV0_SWDS1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                              0x0100L
#define BIF_CFG_DEV0_SWDS1_STATUS__DEVSEL_TIMING_MASK                                                         0x0600L
#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                   0x0800L
#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                 0x1000L
#define BIF_CFG_DEV0_SWDS1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                 0x2000L
#define BIF_CFG_DEV0_SWDS1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                 0x4000L
#define BIF_CFG_DEV0_SWDS1_STATUS__PARITY_ERROR_DETECTED_MASK                                                 0x8000L
//BIF_CFG_DEV0_SWDS1_REVISION_ID
#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                   0x4
#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MINOR_REV_ID_MASK                                                     0x0FL
#define BIF_CFG_DEV0_SWDS1_REVISION_ID__MAJOR_REV_ID_MASK                                                     0xF0L
//BIF_CFG_DEV0_SWDS1_PROG_INTERFACE
#define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                0xFFL
//BIF_CFG_DEV0_SWDS1_SUB_CLASS
#define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_SUB_CLASS__SUB_CLASS_MASK                                                          0xFFL
//BIF_CFG_DEV0_SWDS1_BASE_CLASS
#define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_BASE_CLASS__BASE_CLASS_MASK                                                        0xFFL
//BIF_CFG_DEV0_SWDS1_CACHE_LINE
#define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_SWDS1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                   0xFFL
//BIF_CFG_DEV0_SWDS1_LATENCY
#define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_LATENCY__LATENCY_TIMER_MASK                                                        0xFFL
//BIF_CFG_DEV0_SWDS1_HEADER
#define BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE__SHIFT                                                         0x0
#define BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE__SHIFT                                                         0x7
#define BIF_CFG_DEV0_SWDS1_HEADER__HEADER_TYPE_MASK                                                           0x7FL
#define BIF_CFG_DEV0_SWDS1_HEADER__DEVICE_TYPE_MASK                                                           0x80L
//BIF_CFG_DEV0_SWDS1_BIST
#define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP__SHIFT                                                             0x0
#define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT__SHIFT                                                             0x6
#define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP__SHIFT                                                              0x7
#define BIF_CFG_DEV0_SWDS1_BIST__BIST_COMP_MASK                                                               0x0FL
#define BIF_CFG_DEV0_SWDS1_BIST__BIST_STRT_MASK                                                               0x40L
#define BIF_CFG_DEV0_SWDS1_BIST__BIST_CAP_MASK                                                                0x80L
//BIF_CFG_DEV0_SWDS1_BASE_ADDR_1
#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_BASE_ADDR_1__BASE_ADDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                       0x8
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                         0x10
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                             0x18
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                           0x000000FFL
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                         0x0000FF00L
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                           0x00FF0000L
#define BIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                               0xFF000000L
//BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                 0x0
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                0x8
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                     0xc
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                   0x000FL
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_BASE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                  0x0F00L
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT__IO_LIMIT_MASK                                                       0xF000L
//BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__CAP_LIST__SHIFT                                                  0x4
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                         0x7
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                  0x8
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                             0x9
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                       0xb
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                     0xc
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                     0xd
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                     0xe
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__CAP_LIST_MASK                                                    0x0010L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PCI_66_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                           0x0080L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                    0x0100L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                               0x0600L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                         0x0800L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                       0x1000L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                       0x2000L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                       0x4000L
#define BIF_CFG_DEV0_SWDS1_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                              0x4
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                              0x10
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                             0x14
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                 0x0000000FL
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                0x0000FFF0L
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                        0x4
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                        0x10
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                           0x0000000FL
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                          0x0000FFF0L
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER
#define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                          0x0
#define BIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                            0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                            0x10
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                               0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                              0xFFFF0000L
//BIF_CFG_DEV0_SWDS1_CAP_PTR
#define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR__SHIFT                                                            0x0
#define BIF_CFG_DEV0_SWDS1_CAP_PTR__CAP_PTR_MASK                                                              0x000000FFL
//BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE
#define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                0xFFL
//BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN
#define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                  0xFFL
//BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                    0x1
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                     0x3
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                    0x4
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                          0x5
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                        0x6
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                0x7
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                           0x0001L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                      0x0002L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                       0x0008L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                      0x0010L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                            0x0020L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                          0x0040L
#define BIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                  0x0080L
//BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_SWDS1_PMI_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_SWDS1_PMI_CAP
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION__SHIFT                                                            0x0
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK__SHIFT                                                          0x3
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                  0x5
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT__SHIFT                                                         0x9
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT__SHIFT                                                         0xa
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT__SHIFT                                                        0xb
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__VERSION_MASK                                                              0x0007L
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_CLOCK_MASK                                                            0x0008L
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                    0x0020L
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__AUX_CURRENT_MASK                                                          0x01C0L
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D1_SUPPORT_MASK                                                           0x0200L
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__D2_SUPPORT_MASK                                                           0x0400L
#define BIF_CFG_DEV0_SWDS1_PMI_CAP__PME_SUPPORT_MASK                                                          0xF800L
//BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                              0x3
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                     0x8
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                0x9
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                 0xf
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                              0x16
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                 0x17
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                   0x18
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                  0x00000003L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                0x00000008L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_EN_MASK                                                       0x00000100L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                  0x00001E00L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                   0x00006000L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                   0x00008000L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                0x00400000L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                   0x00800000L
#define BIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                     0xFF000000L
//BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_SWDS1_PCIE_CAP
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                       0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                  0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                   0x9
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__VERSION_MASK                                                             0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__DEVICE_TYPE_MASK                                                         0x00F0L
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                    0x0100L
#define BIF_CFG_DEV0_SWDS1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                     0x3E00L
//BIF_CFG_DEV0_SWDS1_DEVICE_CAP
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                    0x3
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                    0x5
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                          0x6
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                           0x9
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                        0xf
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                       0x12
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                       0x1a
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                     0x1c
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                               0x00000007L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                      0x00000018L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__EXTENDED_TAG_MASK                                                      0x00000020L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                            0x000001C0L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                             0x00000E00L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                          0x00008000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                         0x03FC0000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                         0x0C000000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP__FLR_CAPABLE_MASK                                                       0x10000000L
//BIF_CFG_DEV0_SWDS1_DEVICE_CNTL
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                    0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                               0x1
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                   0x2
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                               0x5
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                0x8
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                0x9
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                0xa
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                    0xb
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                          0xc
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                            0xf
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                      0x0001L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                 0x0002L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                     0x0004L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                   0x0010L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                 0x00E0L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                  0x0100L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                  0x0200L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                  0x0400L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                      0x0800L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                            0x7000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                              0x8000L
//BIF_CFG_DEV0_SWDS1_DEVICE_STATUS
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                0x1
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                    0x2
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                 0x3
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR__SHIFT                                                      0x4
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                            0x5
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__CORR_ERR_MASK                                                       0x0001L
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                  0x0002L
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__FATAL_ERR_MASK                                                      0x0004L
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__USR_DETECTED_MASK                                                   0x0008L
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__AUX_PWR_MASK                                                        0x0010L
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                              0x0020L
//BIF_CFG_DEV0_SWDS1_LINK_CAP
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH__SHIFT                                                        0x4
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                  0xc
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                   0xf
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                            0x12
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                       0x13
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                          0x15
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                       0x16
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER__SHIFT                                                       0x18
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_SPEED_MASK                                                          0x0000000FL
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_WIDTH_MASK                                                          0x000003F0L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PM_SUPPORT_MASK                                                          0x00000C00L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                    0x00007000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                     0x00038000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                              0x00040000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                         0x00080000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                         0x00100000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                            0x00200000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                         0x00400000L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP__PORT_NUMBER_MASK                                                         0xFF000000L
//BIF_CFG_DEV0_SWDS1_LINK_CNTL
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL__SHIFT                                                       0x0
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                0x3
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS__SHIFT                                                         0x4
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                     0x5
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                 0x6
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                    0x7
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                        0x8
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                      0x9
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                        0xa
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                        0xb
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__PM_CONTROL_MASK                                                         0x0003L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                  0x0008L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_DIS_MASK                                                           0x0010L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__RETRAIN_LINK_MASK                                                       0x0020L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                   0x0040L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__EXTENDED_SYNC_MASK                                                      0x0080L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                          0x0100L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                        0x0200L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                          0x0400L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                          0x0800L
//BIF_CFG_DEV0_SWDS1_LINK_STATUS
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                          0x4
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING__SHIFT                                                  0xb
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                 0xc
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE__SHIFT                                                      0xd
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                      0xe
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                      0xf
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                               0x000FL
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                            0x03F0L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_TRAINING_MASK                                                    0x0800L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                   0x1000L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__DL_ACTIVE_MASK                                                        0x2000L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                        0x4000L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                        0x8000L
//BIF_CFG_DEV0_SWDS1_SLOT_CAP
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                            0x1
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                0x2
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                            0x3
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                             0x4
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                  0x5
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                   0x6
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                              0x7
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                              0xf
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                    0x12
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                 0x13
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                 0x00000001L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                              0x00000002L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                  0x00000004L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                              0x00000008L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                               0x00000010L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                    0x00000020L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                     0x00000040L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                0x00007F80L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                0x00018000L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                       0x00020000L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                      0x00040000L
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                   0xFFF80000L
//BIF_CFG_DEV0_SWDS1_SLOT_CNTL
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                           0x0
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                            0x1
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                            0x2
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                       0x3
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                        0x4
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                              0x6
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                               0x8
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                              0xa
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                       0xb
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                              0xc
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                             0x0001L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                              0x0002L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                              0x0004L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                         0x0008L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                          0x0010L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                0x00C0L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                 0x0300L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                0x0400L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                         0x0800L
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                0x1000L
//BIF_CFG_DEV0_SWDS1_SLOT_STATUS
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                             0x1
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                             0x2
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                        0x3
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                              0x4
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                               0x5
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                          0x6
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                   0x7
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                               0x8
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                              0x0001L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                               0x0002L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                               0x0004L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                          0x0008L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                0x0010L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                 0x0020L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                            0x0040L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                     0x0080L
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                 0x0100L
//BIF_CFG_DEV0_SWDS1_DEVICE_CAP2
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                    0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                      0x4
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                       0x5
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                     0x6
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                     0x7
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                     0x8
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                         0x9
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                      0xa
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                  0xb
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                             0xc
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                 0x12
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                   0x14
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                   0x15
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                       0x16
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                      0x0000000FL
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                        0x00000010L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                         0x00000020L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                       0x00000040L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                       0x00000080L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                       0x00000100L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                           0x00000200L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                        0x00000400L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                    0x00000800L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                               0x00003000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                   0x000C0000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                     0x00100000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                     0x00200000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                         0x00C00000L
//BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                               0x4
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                             0x5
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                           0x6
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                      0x7
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                            0x8
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                         0x9
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN__SHIFT                                                        0xa
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                       0xd
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                               0x000FL
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                 0x0010L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                               0x0020L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                             0x0040L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                        0x0080L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                              0x0100L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                           0x0200L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__LTR_EN_MASK                                                          0x0400L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__OBFF_EN_MASK                                                         0x6000L
#define BIF_CFG_DEV0_SWDS1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                     0x8000L
//BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_SWDS1_DEVICE_STATUS2__RESERVED_MASK                                                      0xFFFFL
//BIF_CFG_DEV0_SWDS1_LINK_CAP2
#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                             0x1
#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                              0x8
#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RESERVED__SHIFT                                                         0x9
#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                               0x000000FEL
#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                0x00000100L
#define BIF_CFG_DEV0_SWDS1_LINK_CAP2__RESERVED_MASK                                                           0xFFFFFE00L
//BIF_CFG_DEV0_SWDS1_LINK_CNTL2
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                0x4
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                     0x5
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                           0x6
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                     0x7
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                            0xa
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                  0xb
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                           0xc
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                 0x000FL
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                  0x0010L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                       0x0020L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                             0x0040L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__XMIT_MARGIN_MASK                                                       0x0380L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                              0x0400L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                    0x0800L
#define BIF_CFG_DEV0_SWDS1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                             0xF000L
//BIF_CFG_DEV0_SWDS1_LINK_STATUS2
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                          0x0
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                         0x1
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                   0x2
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                   0x3
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                   0x4
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                            0x0001L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                           0x0002L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                     0x0004L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                     0x0008L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                     0x0010L
#define BIF_CFG_DEV0_SWDS1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                       0x0020L
//BIF_CFG_DEV0_SWDS1_SLOT_CAP2
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED__SHIFT                                                         0x0
#define BIF_CFG_DEV0_SWDS1_SLOT_CAP2__RESERVED_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_SLOT_CNTL2
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_SLOT_CNTL2__RESERVED_MASK                                                          0xFFFFL
//BIF_CFG_DEV0_SWDS1_SLOT_STATUS2
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_SLOT_STATUS2__RESERVED_MASK                                                        0xFFFFL
//BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
#define BIF_CFG_DEV0_SWDS1_MSI_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
//BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                        0x0
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                 0x1
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                  0x4
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                     0x7
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                     0x8
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_EN_MASK                                                          0x0001L
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                   0x000EL
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                    0x0070L
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                       0x0080L
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                       0x0100L
//BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                            0x2
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                              0xFFFFFFFCL
//BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA__MSI_DATA_MASK                                                        0x0000FFFFL
//BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_SWDS1_SSID_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_SWDS1_SSID_CAP
#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                      0x10
#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_SSID_CAP__SUBSYSTEM_ID_MASK                                                        0xFFFF0000L
//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                           0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                          0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                             0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                            0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                              0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                            0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                              0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                            0xa
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                           0x00000007L
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                              0x00000070L
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                0x00000300L
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                              0x00000C00L
//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                           0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                  0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                            0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                              0x000EL
//BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                      0x0001L
//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                       0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                           0x000000FFL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                     0x00008000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                         0x003F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                  0xFF000000L
//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                     0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                 0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                               0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                           0x1f
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                         0x00000001L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                       0x000000FEL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                   0x00010000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                       0x000E0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                 0x07000000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                             0x80000000L
//BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                             0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                            0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                               0x0001L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                              0x0002L
//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                       0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                           0x000000FFL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                     0x00008000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                         0x003F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                  0xFF000000L
//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                     0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                 0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                               0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                           0x1f
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                         0x00000001L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                       0x000000FEL
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                   0x00010000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                       0x000E0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                 0x07000000L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                             0x80000000L
//BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                             0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                            0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                               0x0001L
#define BIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                              0x0002L
//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                     0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                     0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                      0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                   0x5
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                      0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                       0xd
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                    0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                     0x11
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                      0x12
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                     0x13
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                               0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                0x15
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                               0x16
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                               0x17
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                      0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                       0x19
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                        0x00000010L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                     0x00000020L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                        0x00001000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                         0x00002000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                    0x00004000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                  0x00008000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                      0x00010000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                       0x00020000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                        0x00040000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                       0x00080000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                 0x00100000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                  0x00200000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                 0x00400000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                 0x00800000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                        0x01000000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                         0x02000000L
//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                          0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                       0x5
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                          0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                           0xd
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                        0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                         0x11
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                          0x12
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                         0x13
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                   0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                    0x15
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                   0x16
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                   0x17
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                          0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                           0x19
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                            0x00000010L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                         0x00000020L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                            0x00001000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                             0x00002000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                        0x00004000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                      0x00008000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                          0x00010000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                           0x00020000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                            0x00040000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                           0x00080000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                     0x00100000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                      0x00200000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                     0x00400000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                     0x00800000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                            0x01000000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                             0x02000000L
//BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                  0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                               0x5
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                  0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                   0xd
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                              0xe
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                            0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                 0x11
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                  0x12
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                 0x13
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                           0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                            0x15
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                           0x16
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                           0x17
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                  0x18
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                   0x19
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                    0x00000010L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                 0x00000020L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                    0x00001000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                     0x00002000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                0x00004000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                              0x00008000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                  0x00010000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                   0x00020000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                    0x00040000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                   0x00080000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                             0x00100000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                              0x00200000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                             0x00400000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                             0x00800000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                    0x01000000L
#define BIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                     0x02000000L
//BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                        0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                        0x6
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                       0x7
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                            0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                           0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                          0xd
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                   0xe
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                   0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                          0x00000001L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                          0x00000040L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                         0x00000080L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                              0x00000100L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                             0x00001000L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                            0x00002000L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                     0x00004000L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                     0x00008000L
//BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                            0x6
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                           0x7
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                               0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                              0xd
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                       0xe
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                       0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                              0x00000001L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                              0x00000040L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                             0x00000080L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                  0x00000100L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                 0x00001000L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                0x00002000L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                         0x00004000L
#define BIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                         0x00008000L
//BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                        0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                         0x5
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                       0x7
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                        0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                   0x9
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                    0xa
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                               0xb
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                          0x0000001FL
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                           0x00000020L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                            0x00000040L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                         0x00000080L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                          0x00000100L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                     0x00000200L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                      0x00000400L
#define BIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                 0x00000800L
//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                        0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                            0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                              0xFFFFFFFFL
//BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                       0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                               0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                   0x2
#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                         0x00000001L
#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                 0x00000002L
#define BIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3__RESERVED_MASK                                                     0xFFFFFFFCL
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                              0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                            0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                              0xFFFF0000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                    0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT               0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                      0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                 0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT                                     0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                      0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                 0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                        0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                   0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK                                       0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                             0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                          0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                          0x2
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                       0x3
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                           0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                            0x5
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                         0x6
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                    0x8
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                               0x0001L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                            0x0002L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                            0x0004L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                         0x0008L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                             0x0010L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                              0x0020L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                           0x0040L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                      0xFF00L
//BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                         0x0
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                      0x2
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                   0x3
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                           0x0001L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                        0x0004L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                     0x0008L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                       0x0040L


// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC
//BIF_BX_PF3_MM_INDEX
#define BIF_BX_PF3_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
#define BIF_BX_PF3_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
#define BIF_BX_PF3_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
#define BIF_BX_PF3_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
//BIF_BX_PF3_MM_DATA
#define BIF_BX_PF3_MM_DATA__MM_DATA__SHIFT                                                                    0x0
#define BIF_BX_PF3_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
//BIF_BX_PF3_MM_INDEX_HI
#define BIF_BX_PF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
#define BIF_BX_PF3_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC
//BIF_BX_PF1_SYSHUB_INDEX_OVLP
#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT                                                    0x0
#define BIF_BX_PF1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK                                                      0x003FFFFFL
//BIF_BX_PF1_SYSHUB_DATA_OVLP
#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT                                                       0x0
#define BIF_BX_PF1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK                                                         0xFFFFFFFFL
//BIF_BX_PF1_PCIE_INDEX
#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX__SHIFT                                                              0x0
#define BIF_BX_PF1_PCIE_INDEX__PCIE_INDEX_MASK                                                                0xFFFFFFFFL
//BIF_BX_PF1_PCIE_DATA
#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA__SHIFT                                                                0x0
#define BIF_BX_PF1_PCIE_DATA__PCIE_DATA_MASK                                                                  0xFFFFFFFFL
//BIF_BX_PF1_PCIE_INDEX2
#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                            0x0
#define BIF_BX_PF1_PCIE_INDEX2__PCIE_INDEX2_MASK                                                              0xFFFFFFFFL
//BIF_BX_PF1_PCIE_DATA2
#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2__SHIFT                                                              0x0
#define BIF_BX_PF1_PCIE_DATA2__PCIE_DATA2_MASK                                                                0xFFFFFFFFL
//BIF_BX_PF1_SBIOS_SCRATCH_0
#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT                                                   0x0
#define BIF_BX_PF1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW_MASK                                                     0xFFFFFFFFL
//BIF_BX_PF1_SBIOS_SCRATCH_1
#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT                                                   0x0
#define BIF_BX_PF1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW_MASK                                                     0xFFFFFFFFL
//BIF_BX_PF1_SBIOS_SCRATCH_2
#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT                                                   0x0
#define BIF_BX_PF1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW_MASK                                                     0xFFFFFFFFL
//BIF_BX_PF1_SBIOS_SCRATCH_3
#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT                                                   0x0
#define BIF_BX_PF1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW_MASK                                                     0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_0
#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_1
#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_2
#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_3
#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_4
#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_5
#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_6
#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_7
#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_8
#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_9
#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                      0x0
#define BIF_BX_PF1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                        0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_10
#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                    0x0
#define BIF_BX_PF1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                      0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_11
#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                    0x0
#define BIF_BX_PF1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                      0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_12
#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                    0x0
#define BIF_BX_PF1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                      0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_13
#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                    0x0
#define BIF_BX_PF1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                      0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_14
#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                    0x0
#define BIF_BX_PF1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                      0xFFFFFFFFL
//BIF_BX_PF1_BIOS_SCRATCH_15
#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                    0x0
#define BIF_BX_PF1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                      0xFFFFFFFFL
//BIF_BX_PF1_BIF_RLC_INTR_CNTL
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT                                                 0x0
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT                                          0x1
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT                                                0x2
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT                                           0x3
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE_MASK                                                   0x00000001L
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED_MASK                                            0x00000002L
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR_MASK                                                  0x00000004L
#define BIF_BX_PF1_BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION_MASK                                             0x00000008L
//BIF_BX_PF1_BIF_VCE_INTR_CNTL
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT                                                 0x0
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT                                          0x1
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT                                                0x2
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT                                           0x3
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE_MASK                                                   0x00000001L
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED_MASK                                            0x00000002L
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR_MASK                                                  0x00000004L
#define BIF_BX_PF1_BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION_MASK                                             0x00000008L
//BIF_BX_PF1_BIF_UVD_INTR_CNTL
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT                                                 0x0
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT                                          0x1
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT                                                0x2
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT                                           0x3
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE_MASK                                                   0x00000001L
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED_MASK                                            0x00000002L
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR_MASK                                                  0x00000004L
#define BIF_BX_PF1_BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION_MASK                                             0x00000008L
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                      0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                        0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                          0x000FFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL
#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                    0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                      0x000000FFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                              0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                0xFFFFFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                  0xFFFFFFFFL
//BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                              0x0
#define BIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                0xFFFFFFFFL


// addressBlock: nbio_nbif_rcc_strap_BIFDEC1
//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L


// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1
//RCC_PF_0_1_RCC_ERR_LOG
#define RCC_PF_0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                                     0x0
#define RCC_PF_0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                            0x1
#define RCC_PF_0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                       0x00000001L
#define RCC_PF_0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                              0x00000002L
//RCC_PF_0_1_RCC_DOORBELL_APER_EN
#define RCC_PF_0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                          0x0
#define RCC_PF_0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                            0x00000001L
//RCC_PF_0_1_RCC_CONFIG_MEMSIZE
#define RCC_PF_0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                                  0x0
#define RCC_PF_0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                                    0xFFFFFFFFL
//RCC_PF_0_1_RCC_CONFIG_RESERVED
#define RCC_PF_0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                                0x0
#define RCC_PF_0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER
#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                            0x0
#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                                 0x1f
#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                              0x00000001L
#define RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                                   0x80000000L


// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1
//BIF_BX_PF1_BIF_MM_INDACCESS_CNTL
#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                             0x1
#define BIF_BX_PF1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                               0x00000002L
//BIF_BX_PF1_BUS_CNTL
#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP__SHIFT                                                            0x3
#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN__SHIFT                                                            0x4
#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT                                                          0x5
#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                     0x6
#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                     0x7
#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC__SHIFT                                                                 0xa
#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC__SHIFT                                                                 0xd
#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                             0x10
#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                             0x11
#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                            0x12
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT                                             0x13
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT                                             0x14
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT                                           0x15
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT                                                0x16
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT                                                0x17
#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT                                                       0x18
#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                       0x19
#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT                                               0x1b
#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT                                               0x1c
#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                  0x1d
#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                       0x1e
#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                       0x1f
#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_EP_MASK                                                              0x00000008L
#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_DN_MASK                                                              0x00000010L
#define BIF_BX_PF1_BUS_CNTL__PMI_INT_DIS_SWUS_MASK                                                            0x00000020L
#define BIF_BX_PF1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                       0x00000040L
#define BIF_BX_PF1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                       0x00000080L
#define BIF_BX_PF1_BUS_CNTL__SET_AZ_TC_MASK                                                                   0x00001C00L
#define BIF_BX_PF1_BUS_CNTL__SET_MC_TC_MASK                                                                   0x0000E000L
#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                               0x00010000L
#define BIF_BX_PF1_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                               0x00020000L
#define BIF_BX_PF1_BUS_CNTL__RD_STALL_IO_WR_MASK                                                              0x00040000L
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK                                               0x00080000L
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK                                               0x00100000L
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK                                             0x00200000L
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK                                                  0x00400000L
#define BIF_BX_PF1_BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK                                                  0x00800000L
#define BIF_BX_PF1_BUS_CNTL__UR_OVRD_FOR_ECRC_EN_MASK                                                         0x01000000L
#define BIF_BX_PF1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                         0x02000000L
#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK                                                 0x08000000L
#define BIF_BX_PF1_BUS_CNTL__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK                                                 0x10000000L
#define BIF_BX_PF1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                    0x20000000L
#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                         0x40000000L
#define BIF_BX_PF1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                         0x80000000L
//BIF_BX_PF1_BIF_SCRATCH0
#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                          0x0
#define BIF_BX_PF1_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                            0xFFFFFFFFL
//BIF_BX_PF1_BIF_SCRATCH1
#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                          0x0
#define BIF_BX_PF1_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                            0xFFFFFFFFL
//BIF_BX_PF1_BX_RESET_EN
#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN__SHIFT                                                           0x0
#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN__SHIFT                                                           0x1
#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN__SHIFT                                                           0x2
#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN__SHIFT                                                           0x8
#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                               0x10
#define BIF_BX_PF1_BX_RESET_EN__COR_RESET_EN_MASK                                                             0x00000001L
#define BIF_BX_PF1_BX_RESET_EN__REG_RESET_EN_MASK                                                             0x00000002L
#define BIF_BX_PF1_BX_RESET_EN__STY_RESET_EN_MASK                                                             0x00000004L
#define BIF_BX_PF1_BX_RESET_EN__FLR_TWICE_EN_MASK                                                             0x00000100L
#define BIF_BX_PF1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                 0x00010000L
//BIF_BX_PF1_MM_CFGREGS_CNTL
#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                    0x0
#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                     0x6
#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                    0x1f
#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                      0x00000007L
#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                       0x000000C0L
#define BIF_BX_PF1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                      0x80000000L
//BIF_BX_PF1_BX_RESET_CNTL
#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                        0x0
#define BIF_BX_PF1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                          0x00000001L
//BIF_BX_PF1_INTERRUPT_CNTL
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                0x0
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                      0x1
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                  0x3
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                    0x4
#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                       0x8
#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                              0xf
#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                            0x10
#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                0x11
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                  0x00000001L
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                        0x00000002L
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                    0x00000008L
#define BIF_BX_PF1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                      0x000000F0L
#define BIF_BX_PF1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                         0x00000100L
#define BIF_BX_PF1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                0x00008000L
#define BIF_BX_PF1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                              0x00010000L
#define BIF_BX_PF1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                  0x00020000L
//BIF_BX_PF1_INTERRUPT_CNTL2
#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                   0x0
#define BIF_BX_PF1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_BX_PF1_CLKREQB_PAD_CNTL
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                     0x0
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                   0x1
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                  0x2
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                 0x3
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                   0x5
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                   0x6
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                   0x7
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                   0x8
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                 0x9
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                  0xa
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                0xb
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                               0xc
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                     0xd
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                       0x00000001L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                     0x00000002L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                    0x00000004L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                   0x00000018L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                     0x00000020L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                     0x00000040L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                     0x00000080L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                     0x00000100L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                   0x00000200L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                    0x00000400L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                  0x00000800L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                 0x00001000L
#define BIF_BX_PF1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                       0x00002000L
//BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                       0x0
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                       0x1
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                       0x2
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                       0x3
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                   0xc
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                       0xd
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                        0xf
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT                                     0x11
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT                                     0x12
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                0x18
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                         0x00000001L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                         0x00000002L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                         0x00000004L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                         0x00000008L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                     0x00001000L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                         0x00002000L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                          0x00008000L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS_MASK                                       0x00020000L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS_MASK                                       0x00040000L
#define BIF_BX_PF1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                  0x01000000L
//BIF_BX_PF1_BIF_DOORBELL_CNTL
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                    0x0
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                  0x1
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                 0x2
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                      0x3
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                              0x4
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                               0x18
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                            0x19
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                            0x1a
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                            0x1b
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                      0x00000001L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                    0x00000002L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                   0x00000004L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                        0x00000008L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                0x00000010L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                 0x01000000L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                              0x02000000L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                              0x04000000L
#define BIF_BX_PF1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                              0x08000000L
//BIF_BX_PF1_BIF_DOORBELL_INT_CNTL
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                    0x0
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT                                    0x1
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                     0x10
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT                                     0x11
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                      0x00000001L
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS_MASK                                      0x00000002L
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                       0x00010000L
#define BIF_BX_PF1_BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR_MASK                                       0x00020000L
//BIF_BX_PF1_BIF_FB_EN
#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN__SHIFT                                                               0x0
#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                              0x1
#define BIF_BX_PF1_BIF_FB_EN__FB_READ_EN_MASK                                                                 0x00000001L
#define BIF_BX_PF1_BIF_FB_EN__FB_WRITE_EN_MASK                                                                0x00000002L
//BIF_BX_PF1_BIF_BUSY_DELAY_CNTR
#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT                                                      0x0
#define BIF_BX_PF1_BIF_BUSY_DELAY_CNTR__DELAY_CNT_MASK                                                        0x0000003FL
//BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF
#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                     0x0
#define BIF_BX_PF1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                       0x0000FFFFL
//BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF
#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                     0x0
#define BIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                       0x0000FFFFL
//BIF_BX_PF1_BACO_CNTL
#define BIF_BX_PF1_BACO_CNTL__BACO_EN__SHIFT                                                                  0x0
#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT                                                     0x1
#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                            0x2
#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                           0x3
#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                       0x5
#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                       0x6
#define BIF_BX_PF1_BACO_CNTL__BACO_MODE__SHIFT                                                                0x8
#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                      0x9
#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                           0x1f
#define BIF_BX_PF1_BACO_CNTL__BACO_EN_MASK                                                                    0x00000001L
#define BIF_BX_PF1_BACO_CNTL__BACO_BIF_LCLK_SWITCH_MASK                                                       0x00000002L
#define BIF_BX_PF1_BACO_CNTL__BACO_DUMMY_EN_MASK                                                              0x00000004L
#define BIF_BX_PF1_BACO_CNTL__BACO_POWER_OFF_MASK                                                             0x00000008L
#define BIF_BX_PF1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                         0x00000020L
#define BIF_BX_PF1_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                         0x00000040L
#define BIF_BX_PF1_BACO_CNTL__BACO_MODE_MASK                                                                  0x00000100L
#define BIF_BX_PF1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                        0x00000200L
#define BIF_BX_PF1_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                             0x80000000L
//BIF_BX_PF1_BIF_BACO_EXIT_TIME0
#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                       0x0
#define BIF_BX_PF1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                         0x000FFFFFL
//BIF_BX_PF1_BIF_BACO_EXIT_TIMER1
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                      0x0
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                         0x18
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR__SHIFT                     0x19
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                              0x1a
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                        0x1b
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                         0x1c
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                 0x1d
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                  0x1f
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                        0x000FFFFFL
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                           0x01000000L
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_ENDING_AUTO_BY_RSMU_INTR_CLR_MASK                       0x02000000L
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                0x04000000L
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                          0x08000000L
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                           0x10000000L
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                   0x60000000L
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                    0x80000000L
//BIF_BX_PF1_BIF_BACO_EXIT_TIMER2
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                      0x0
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                        0x000FFFFFL
//BIF_BX_PF1_BIF_BACO_EXIT_TIMER3
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                  0x0
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                    0x000FFFFFL
//BIF_BX_PF1_BIF_BACO_EXIT_TIMER4
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                   0x0
#define BIF_BX_PF1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                     0x000FFFFFL
//BIF_BX_PF1_MEM_TYPE_CNTL
#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                     0x0
#define BIF_BX_PF1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                       0x00000001L
//BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS
#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT                                       0x0
#define BIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF_MASK                                         0x00000001L
//BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT                                       0x1e
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT                                     0x1f
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER_MASK                                          0x0003FFFCL
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN_MASK                                         0x40000000L
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN_MASK                                       0x80000000L
//BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT                                        0x2
#define BIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER_MASK                                          0x0003FFFCL
//BIF_BX_PF1_BIF_VDDGFX_FB_CMP
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT                                             0x0
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT                                           0x1
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT                                            0x2
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT                                          0x3
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT                                             0x4
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT                                           0x5
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN_MASK                                               0x00000001L
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN_MASK                                             0x00000002L
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN_MASK                                              0x00000004L
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN_MASK                                            0x00000008L
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN_MASK                                               0x00000010L
#define BIF_BX_PF1_BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN_MASK                                             0x00000020L
//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT                                0x2
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT                                   0x1f
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER_MASK                                  0x00000FFCL
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN_MASK                                     0x80000000L
//BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT                                0x2
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER_MASK                                  0x00000FFCL
//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT                                0x2
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT                                   0x1f
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER_MASK                                  0x00000FFCL
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN_MASK                                     0x80000000L
//BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT                                0x2
#define BIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER_MASK                                  0x00000FFCL
//BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL
#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                   0x2
#define BIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                     0x0007FFFCL
//BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL
#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                   0x2
#define BIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                     0x0007FFFCL
//BIF_BX_PF1_BIF_RB_CNTL
#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                              0x0
#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                0x1
#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                  0x8
#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                   0x9
#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                            0x11
#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                    0x1f
#define BIF_BX_PF1_BIF_RB_CNTL__RB_ENABLE_MASK                                                                0x00000001L
#define BIF_BX_PF1_BIF_RB_CNTL__RB_SIZE_MASK                                                                  0x0000003EL
#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                    0x00000100L
#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                     0x00003E00L
#define BIF_BX_PF1_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                              0x00020000L
#define BIF_BX_PF1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                      0x80000000L
//BIF_BX_PF1_BIF_RB_BASE
#define BIF_BX_PF1_BIF_RB_BASE__ADDR__SHIFT                                                                   0x0
#define BIF_BX_PF1_BIF_RB_BASE__ADDR_MASK                                                                     0xFFFFFFFFL
//BIF_BX_PF1_BIF_RB_RPTR
#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET__SHIFT                                                                 0x2
#define BIF_BX_PF1_BIF_RB_RPTR__OFFSET_MASK                                                                   0x0003FFFCL
//BIF_BX_PF1_BIF_RB_WPTR
#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                        0x0
#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET__SHIFT                                                                 0x2
#define BIF_BX_PF1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                          0x00000001L
#define BIF_BX_PF1_BIF_RB_WPTR__OFFSET_MASK                                                                   0x0003FFFCL
//BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI
#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                           0x0
#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                             0x000000FFL
//BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO
#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                           0x2
#define BIF_BX_PF1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                             0xFFFFFFFCL
//BIF_BX_PF1_MAILBOX_INDEX
#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                        0x0
#define BIF_BX_PF1_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                          0x0000001FL
//BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE
#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT                                        0x0
#define BIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE_MASK                                          0x0000000FL
//BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE
#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT                                        0x0
#define BIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE_MASK                                          0x0000000FL
//BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE
#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT                              0x0
#define BIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE_MASK                                0x0000000FL
//BIF_BX_PF1_BIF_PERSTB_PAD_CNTL
#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                0x0
#define BIF_BX_PF1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                  0x0000FFFFL
//BIF_BX_PF1_BIF_PX_EN_PAD_CNTL
#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                  0x0
#define BIF_BX_PF1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                    0x000000FFL
//BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL
#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                          0x0
#define BIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                            0x000000FFL
//BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL
#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                              0x0
#define BIF_BX_PF1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                0x00FFFFFFL


// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
//BIF_BX_PF1_BIF_BME_STATUS
#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
//BIF_BX_PF1_BIF_TRANS_PENDING
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
//BIF_BX_PF1_MAILBOX_CONTROL
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
//BIF_BX_PF1_MAILBOX_INT_CNTL
#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
//BIF_BX_PF1_BIF_VMHV_MAILBOX
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L


// addressBlock: nbio_nbif_rcc_shadow_reg_shadowdec
//SHADOW_COMMAND
#define SHADOW_COMMAND__IOEN_UP__SHIFT                                                                        0x0
#define SHADOW_COMMAND__MEMEN_UP__SHIFT                                                                       0x1
#define SHADOW_COMMAND__IOEN_UP_MASK                                                                          0x0001L
#define SHADOW_COMMAND__MEMEN_UP_MASK                                                                         0x0002L
//SHADOW_BASE_ADDR_1
#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT                                                                    0x0
#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK                                                                      0xFFFFFFFFL
//SHADOW_BASE_ADDR_2
#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT                                                                    0x0
#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK                                                                      0xFFFFFFFFL
//SHADOW_SUB_BUS_NUMBER_LATENCY
#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT                                                0x8
#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT                                                  0x10
#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK                                                  0x0000FF00L
#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK                                                    0x00FF0000L
//SHADOW_IO_BASE_LIMIT
#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT                                                               0x4
#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT                                                              0xc
#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK                                                                 0x00F0L
#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK                                                                0xF000L
//SHADOW_MEM_BASE_LIMIT
#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                           0x0
#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT                                                       0x4
#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                          0x10
#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT                                                      0x14
#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                             0x0000000FL
#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK                                                         0x0000FFF0L
#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                            0x000F0000L
#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK                                                        0xFFF00000L
//SHADOW_PREF_BASE_LIMIT
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                     0x0
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT                                                 0x4
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                    0x10
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT                                                0x14
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                       0x0000000FL
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK                                                   0x0000FFF0L
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                      0x000F0000L
#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK                                                  0xFFF00000L
//SHADOW_PREF_BASE_UPPER
#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT                                                     0x0
#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK                                                       0xFFFFFFFFL
//SHADOW_PREF_LIMIT_UPPER
#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT                                                   0x0
#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK                                                     0xFFFFFFFFL
//SHADOW_IO_BASE_LIMIT_HI
#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT                                                      0x0
#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT                                                     0x10
#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK                                                        0x0000FFFFL
#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK                                                       0xFFFF0000L
//SHADOW_IRQ_BRIDGE_CNTL
#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT                                                              0x2
#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT                                                              0x3
#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT                                                             0x4
#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT                                                 0x6
#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK                                                                0x0004L
#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK                                                                0x0008L
#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK                                                               0x0010L
#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK                                                   0x0040L
//SUC_INDEX
#define SUC_INDEX__SUC_INDEX__SHIFT                                                                           0x0
#define SUC_INDEX__SUC_INDEX_MASK                                                                             0xFFFFFFFFL
//SUC_DATA
#define SUC_DATA__SUC_DATA__SHIFT                                                                             0x0
#define SUC_DATA__SUC_DATA_MASK                                                                               0xFFFFFFFFL


// addressBlock: nbio_nbif_rcc_ep_dev0_RCCPORTDEC
//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
//RCC_EP_DEV0_1_EP_PCIE_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L


// addressBlock: nbio_nbif_rcc_dwn_dev0_RCCPORTDEC
//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
//RCC_DWN_DEV0_1_DN_PCIE_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L


// addressBlock: nbio_nbif_rcc_dwnp_dev0_RCCPORTDEC
//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL


// addressBlock: nbio_nbif_rcc_strap_rcc_strap_internal
//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L


// addressBlock: nbio_nbif_bif_bx_pf_SUMDEC
//SUM_INDEX
#define SUM_INDEX__SUM_INDEX__SHIFT                                                                           0x0
#define SUM_INDEX__SUM_INDEX_MASK                                                                             0xFFFFFFFFL
//SUM_DATA
#define SUM_DATA__SUM_DATA__SHIFT                                                                             0x0
#define SUM_DATA__SUM_DATA_MASK                                                                               0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_misc_bif_misc_regblk
//MISC_SCRATCH
#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT                                                                    0x0
#define MISC_SCRATCH__MISC_SCRATCH0_MASK                                                                      0xFFFFFFFFL
//INTR_LINE_POLARITY
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT                                                    0x0
#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK                                                      0x000000FFL
//INTR_LINE_ENABLE
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT                                                        0x0
#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK                                                          0x000000FFL
//OUTSTANDING_VC_ALLOC
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x0
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x2
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT                                                0x4
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT                                                0x6
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT                                                0x8
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT                                                0xa
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT                                                0xc
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT                                                0xe
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT                                                     0x10
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x18
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x1a
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT                                                     0x1c
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK                                                  0x00000003L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0000000CL
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK                                                  0x00000030L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK                                                  0x000000C0L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK                                                  0x00000300L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK                                                  0x00000C00L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK                                                  0x00003000L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK                                                  0x0000C000L
#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK                                                       0x000F0000L
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK                                                  0x03000000L
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0C000000L
#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK                                                       0xF0000000L
//BIFC_MISC_CTRL0
#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT                                                    0x0
#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT                                                     0x1
#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT                                                     0x8
#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT                                                            0x9
#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT                                                        0xa
#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT                                                     0x10
#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT                                                     0x11
#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT                                               0x12
#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT                                                              0x13
#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT                                                         0x14
#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT                                                      0x18
#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT                                                             0x19
#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT                                                               0x1a
#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT                                                       0x1b
#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT                                                              0x1c
#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT                                                            0x1f
#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK                                                      0x00000001L
#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK                                                       0x00000006L
#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK                                                       0x00000100L
#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_MASK                                                              0x00000200L
#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK                                                          0x00000400L
#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK                                                       0x00010000L
#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK                                                       0x00020000L
#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK                                                 0x00040000L
#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK                                                                0x00080000L
#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK                                                           0x00100000L
#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK                                                        0x01000000L
#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK                                                               0x02000000L
#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK                                                                 0x04000000L
#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK                                                         0x08000000L
#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK                                                                0x10000000L
#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK                                                              0x80000000L
//BIFC_MISC_CTRL1
#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT                                                    0x0
#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT                                                         0x1
#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT                                                         0x2
#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT                                                    0x3
#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT                                                      0x4
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT                                           0x5
#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT                                                          0x6
#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT                                                          0x7
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT                                                      0x8
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT                                                  0xa
#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT                                                        0xc
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT                                                 0xd
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT                                           0xe
#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT                                                              0xf
#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT                                                       0x10
#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT                                                       0x11
#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT                                                       0x12
#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT                                                       0x13
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT                                           0x14
#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT                                                      0x18
#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT                                                    0x19
#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT                                                      0x1a
#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT                                                    0x1b
#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT                                       0x1c
#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK                                                      0x00000001L
#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK                                                           0x00000002L
#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK                                                           0x00000004L
#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK                                                      0x00000008L
#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK                                                        0x00000010L
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK                                             0x00000020L
#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK                                                            0x00000040L
#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK                                                            0x00000080L
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK                                                        0x00000300L
#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK                                                    0x00000C00L
#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK                                                          0x00001000L
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK                                                   0x00002000L
#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK                                             0x00004000L
#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK                                                                0x00008000L
#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK                                                         0x00010000L
#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK                                                         0x00020000L
#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK                                                         0x00040000L
#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK                                                         0x00080000L
#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK                                             0x00100000L
#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK                                                        0x01000000L
#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK                                                      0x02000000L
#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK                                                        0x04000000L
#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK                                                      0x08000000L
#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK                                         0x10000000L
//BIFC_BME_ERR_LOG
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT                                                       0x0
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT                                                       0x1
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT                                                       0x2
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT                                                       0x3
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT                                                       0x4
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT                                                       0x5
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT                                                       0x6
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT                                                       0x7
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT                                                 0x10
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT                                                 0x11
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT                                                 0x12
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT                                                 0x13
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT                                                 0x14
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT                                                 0x15
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT                                                 0x16
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT                                                 0x17
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0_MASK                                                         0x00000001L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1_MASK                                                         0x00000002L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2_MASK                                                         0x00000004L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3_MASK                                                         0x00000008L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4_MASK                                                         0x00000010L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5_MASK                                                         0x00000020L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6_MASK                                                         0x00000040L
#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7_MASK                                                         0x00000080L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK                                                   0x00010000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK                                                   0x00020000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2_MASK                                                   0x00040000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3_MASK                                                   0x00080000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4_MASK                                                   0x00100000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5_MASK                                                   0x00200000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6_MASK                                                   0x00400000L
#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7_MASK                                                   0x00800000L
//BIFC_RCCBIH_BME_ERR_LOG
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                             0x0
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                             0x1
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT                                             0x2
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT                                             0x3
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT                                             0x4
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT                                             0x5
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT                                             0x6
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT                                             0x7
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                       0x10
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                       0x11
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT                                       0x12
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT                                       0x13
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT                                       0x14
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT                                       0x15
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT                                       0x16
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT                                       0x17
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                               0x00000001L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                               0x00000002L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2_MASK                                               0x00000004L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3_MASK                                               0x00000008L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4_MASK                                               0x00000010L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5_MASK                                               0x00000020L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6_MASK                                               0x00000040L
#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7_MASK                                               0x00000080L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                         0x00010000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                         0x00020000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2_MASK                                         0x00040000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3_MASK                                         0x00080000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4_MASK                                         0x00100000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5_MASK                                         0x00200000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6_MASK                                         0x00400000L
#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7_MASK                                         0x00800000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK                                     0x30000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK                                     0x30000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK                                     0x30000000L
//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT                                    0x0
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT                                   0x2
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT                                     0x6
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT                                    0x8
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT                                    0xa
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT                                   0xc
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT                                    0x10
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT                                   0x12
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT                                     0x16
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT                                    0x18
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT                                    0x1a
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT                                   0x1c
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK                                      0x00000003L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK                                     0x0000000CL
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK                                       0x000000C0L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK                                      0x00000300L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK                                      0x00000C00L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK                                     0x00003000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK                                      0x00030000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK                                     0x000C0000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK                                       0x00C00000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK                                      0x03000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK                                      0x0C000000L
#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK                                     0x30000000L
//NBIF_VWIRE_CTRL
#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT                                                       0x4
#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT                                                                0x8
#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT                                                       0x14
#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT                                                              0x1a
#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK                                                         0x000000F0L
#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK                                                                  0x00000100L
#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK                                                         0x00F00000L
#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK                                                                0x0C000000L
//NBIF_SMN_VWR_VCHG_DIS_CTRL
#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT                                              0x0
#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT                                              0x1
#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT                                              0x2
#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS_MASK                                                0x00000001L
#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS_MASK                                                0x00000002L
#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS_MASK                                                0x00000004L
//NBIF_SMN_VWR_VCHG_RST_CTRL0
#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT                                     0x0
#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT                                     0x1
#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT                                     0x2
#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV_MASK                                       0x00000001L
#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV_MASK                                       0x00000002L
#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV_MASK                                       0x00000004L
//NBIF_SMN_VWR_VCHG_TRIG
#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT                                                 0x0
#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT                                                 0x1
#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT                                                 0x2
#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG_MASK                                                   0x00000001L
#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG_MASK                                                   0x00000002L
#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG_MASK                                                   0x00000004L
//NBIF_SMN_VWR_WTRIG_CNTL
#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT                                                0x0
#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT                                                0x1
#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT                                                0x2
#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS_MASK                                                  0x00000001L
#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS_MASK                                                  0x00000002L
#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS_MASK                                                  0x00000004L
//NBIF_SMN_VWR_VCHG_DIS_CTRL_1
#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT                                0x0
#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT                                0x1
#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT                                0x2
#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV_MASK                                  0x00000001L
#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV_MASK                                  0x00000002L
#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV_MASK                                  0x00000004L
//NBIF_MGCG_CTRL_LCLK
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT                                                         0x0
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT                                                       0x1
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT                                                 0x2
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT                                                    0xa
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT                                                    0xb
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK__SHIFT                                                   0xc
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT                                                    0xd
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK                                                           0x00000001L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK                                                         0x00000002L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK                                                   0x000003FCL
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK                                                      0x00000400L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK                                                      0x00000800L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REGS_DIS_LCLK_MASK                                                     0x00001000L
#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK                                                      0x00002000L
//NBIF_DS_CTRL_LCLK
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT                                                             0x0
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT                                                          0x10
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK                                                               0x00000001L
#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK                                                            0xFFFF0000L
//SMN_MST_CNTL0
#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT                                                                    0x0
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT                                                           0x8
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT                                                           0x9
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT                                                            0xa
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT                                                      0xb
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT                                                      0x10
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT                                                      0x14
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT                                                       0x18
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT                                                 0x1c
#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK                                                                      0x00000003L
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK                                                             0x00000100L
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK                                                             0x00000200L
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK                                                              0x00000400L
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK                                                        0x00000800L
#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK                                                        0x00010000L
#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK                                                        0x00100000L
#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK                                                         0x01000000L
#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK                                                   0x10000000L
//SMN_MST_EP_CNTL1
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT                                                 0x0
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT                                                 0x1
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT                                                 0x2
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT                                                 0x3
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT                                                 0x4
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT                                                 0x5
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT                                                 0x6
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT                                                 0x7
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK                                                   0x00000001L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK                                                   0x00000002L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK                                                   0x00000004L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK                                                   0x00000008L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK                                                   0x00000010L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK                                                   0x00000020L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK                                                   0x00000040L
#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK                                                   0x00000080L
//SMN_MST_EP_CNTL2
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT                                           0x0
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT                                           0x1
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT                                           0x2
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT                                           0x3
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT                                           0x4
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT                                           0x5
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT                                           0x6
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT                                           0x7
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK                                             0x00000001L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK                                             0x00000002L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK                                             0x00000004L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK                                             0x00000008L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK                                             0x00000010L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK                                             0x00000020L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK                                             0x00000040L
#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK                                             0x00000080L
//NBIF_SDP_VWR_VCHG_DIS_CTRL
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT                                           0x0
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT                                           0x1
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT                                           0x2
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT                                           0x3
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT                                           0x4
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT                                           0x5
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT                                           0x6
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT                                           0x7
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT                                           0x18
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK                                             0x00000001L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK                                             0x00000002L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK                                             0x00000004L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK                                             0x00000008L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK                                             0x00000010L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK                                             0x00000020L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK                                             0x00000040L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK                                             0x00000080L
#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK                                             0x01000000L
//NBIF_SDP_VWR_VCHG_RST_CTRL0
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT                                  0x0
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT                                  0x1
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT                                  0x2
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT                                  0x3
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT                                  0x4
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT                                  0x5
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT                                  0x6
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT                                  0x7
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT                                  0x18
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK                                    0x00000001L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK                                    0x00000002L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK                                    0x00000004L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK                                    0x00000008L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK                                    0x00000010L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK                                    0x00000020L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK                                    0x00000040L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK                                    0x00000080L
#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK                                    0x01000000L
//NBIF_SDP_VWR_VCHG_RST_CTRL1
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT                                 0x0
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT                                 0x1
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT                                 0x2
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT                                 0x3
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT                                 0x4
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT                                 0x5
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT                                 0x6
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT                                 0x7
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT                                 0x18
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK                                   0x00000001L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK                                   0x00000002L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK                                   0x00000004L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK                                   0x00000008L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK                                   0x00000010L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK                                   0x00000020L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK                                   0x00000040L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK                                   0x00000080L
#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK                                   0x01000000L
//NBIF_SDP_VWR_VCHG_TRIG
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT                                              0x0
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT                                              0x1
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT                                              0x2
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT                                              0x3
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT                                              0x4
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT                                              0x5
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT                                              0x6
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT                                              0x7
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT                                              0x18
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK                                                0x00000001L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK                                                0x00000002L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK                                                0x00000004L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK                                                0x00000008L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK                                                0x00000010L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK                                                0x00000020L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK                                                0x00000040L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK                                                0x00000080L
#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK                                                0x01000000L
//BME_DUMMY_CNTL_0
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT                                                     0x0
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT                                                     0x2
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT                                                     0x4
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT                                                     0x6
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT                                                     0x8
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT                                                     0xa
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT                                                     0xc
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT                                                     0xe
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK                                                       0x00000003L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK                                                       0x0000000CL
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK                                                       0x00000030L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK                                                       0x000000C0L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK                                                       0x00000300L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK                                                       0x00000C00L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK                                                       0x00003000L
#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK                                                       0x0000C000L
//BIFC_THT_CNTL
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT                                                         0x0
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT                                                         0x4
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT                                                         0x8
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK                                                           0x0000000FL
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK                                                           0x000000F0L
#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK                                                           0x00000F00L
//BIFC_HSTARB_CNTL
#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT                                                                  0x0
#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK                                                                    0x00000003L
//BIFC_GSI_CNTL
#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT                                                            0x0
#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT                                                            0x2
#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT                                                         0x5
#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT                                                      0x6
#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT                                                    0x7
#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT                                                   0x8
#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT                                                      0x9
#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT                                                            0xa
#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT                                                            0xc
#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK                                                              0x00000003L
#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK                                                              0x0000001CL
#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK                                                           0x00000020L
#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK                                                        0x00000040L
#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK                                                      0x00000080L
#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK                                                     0x00000100L
#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK                                                        0x00000200L
#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK                                                              0x00000C00L
#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK                                                              0x00003000L
//BIFC_PCIEFUNC_CNTL
#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT                                                0x0
#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT                                             0x10
#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK                                                  0x0000FFFFL
#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK                                               0x00010000L
//BIFC_SDP_CNTL_0
#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x0
#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x8
#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x10
#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x18
#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK                                                       0x000000FFL
#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK                                                       0x0000FF00L
#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK                                                   0x00FF0000L
#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK                                                   0xFF000000L
//BIFC_SDP_CNTL_1
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT                                                            0x0
#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT                                                            0x1
#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT                                                        0x2
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT                                                        0x3
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                               0x4
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                           0x7
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK                                                              0x00000001L
#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK                                                              0x00000002L
#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK                                                          0x00000004L
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK                                                          0x00000008L
#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                                 0x00000010L
#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                             0x00000080L
//BIFC_PERF_CNTL_0
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT                                                          0x0
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT                                                          0x1
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT                                                       0x8
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT                                                       0x9
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT                                                         0x10
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT                                                         0x18
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK                                                            0x00000001L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK                                                            0x00000002L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK                                                         0x00000100L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK                                                         0x00000200L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK                                                           0x001F0000L
#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK                                                           0x1F000000L
//BIFC_PERF_CNTL_1
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT                                                           0x0
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT                                                           0x1
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT                                                        0x8
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT                                                        0x9
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT                                                          0x10
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT                                                          0x18
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK                                                             0x00000001L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK                                                             0x00000002L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK                                                          0x00000100L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK                                                          0x00000200L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK                                                            0x003F0000L
#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK                                                            0x7F000000L
//BIFC_PERF_CNT_MMIO_RD
#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT                                                  0x0
#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE_MASK                                                    0xFFFFFFFFL
//BIFC_PERF_CNT_MMIO_WR
#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT                                                  0x0
#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE_MASK                                                    0xFFFFFFFFL
//BIFC_PERF_CNT_DMA_RD
#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT                                                    0x0
#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE_MASK                                                      0xFFFFFFFFL
//BIFC_PERF_CNT_DMA_WR
#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT                                                    0x0
#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE_MASK                                                      0xFFFFFFFFL
//NBIF_REGIF_ERRSET_CTRL
#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                         0x0
#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                           0x00000001L
//SMN_MST_EP_CNTL3
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT                                                0x0
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT                                                0x1
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT                                                0x2
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT                                                0x3
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT                                                0x4
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT                                                0x5
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT                                                0x6
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT                                                0x7
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
//SMN_MST_EP_CNTL4
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT                                                0x0
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT                                                0x1
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT                                                0x2
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT                                                0x3
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT                                                0x4
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT                                                0x5
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT                                                0x6
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT                                                0x7
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
//SMN_MST_CNTL1
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT                                                    0x0
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT                                               0x10
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK                                                      0x00000001L
#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK                                                 0x00010000L
//SMN_MST_EP_CNTL5
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT                                         0x0
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT                                         0x1
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT                                         0x2
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT                                         0x3
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT                                         0x4
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT                                         0x5
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT                                         0x6
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT                                         0x7
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK                                           0x00000001L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK                                           0x00000002L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK                                           0x00000004L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK                                           0x00000008L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK                                           0x00000010L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK                                           0x00000020L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK                                           0x00000040L
#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK                                           0x00000080L
//BIF_SELFRING_BUFFER_VID
#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT                                                  0x0
#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT                                                    0x8
#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK                                                    0x000000FFL
#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID_MASK                                                      0x0000FF00L
//BIF_SELFRING_VECTOR_CNTL
#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT                                                0x0
#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT                                                      0x1
#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK                                                  0x00000001L
#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK                                                        0x00000002L
//BIF_GMI_WRR_WEIGHT
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT                                                    0x0
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT                                                      0x8
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT                                                     0x10
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE__SHIFT                                                           0x1f
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT_MASK                                                      0x000000FFL
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT_MASK                                                        0x0000FF00L
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT_MASK                                                       0x00FF0000L
#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_MODE_MASK                                                             0x80000000L


// addressBlock: nbio_nbif_rcc_pfc_amdgfx_RCCPFCDEC
//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT                                           0x0
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT                                           0xa
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT                                             0xf
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT                                        0x10
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT                                        0x1a
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT                                          0x1f
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK                                             0x000003FFL
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK                                             0x00001C00L
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK                                               0x00008000L
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK                                          0x03FF0000L
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK                                          0x1C000000L
#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK                                            0x80000000L
//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE
#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT                                         0x0
#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT                                     0x8
#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK                                           0x00000001L
#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK                                       0x00000100L
//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT                                0x0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT                            0x1
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT                          0x2
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT                              0x3
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT                                0x4
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT                               0x5
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT                         0x6
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT                  0x7
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK                                  0x00000001L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK                              0x00000002L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK                            0x00000004L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK                                0x00000008L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK                                  0x00000010L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK                                 0x00000020L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK                           0x00000040L
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK                    0x00000080L
//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT                                     0x0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK                                       0xFFFFFFFFL
//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT                                     0x0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK                                       0xFFFFFFFFL
//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT                                     0x0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK                                       0xFFFFFFFFL
//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT                                     0x0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK                                       0xFFFFFFFFL
//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT                                    0x0
#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK                                      0xFFFFFFFFL
//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL
#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT                                       0x0
#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT                                0x3
#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK                                         0x00000007L
#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK                                  0x00000008L


// addressBlock: nbio_nbif_rcc_pfc_amdgfxaz_RCCPFCDEC
//RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT                                         0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT                                         0xa
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT                                           0xf
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT                                      0x10
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT                                      0x1a
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT                                        0x1f
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK                                           0x000003FFL
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK                                           0x00001C00L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK                                             0x00008000L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK                                        0x03FF0000L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK                                        0x1C000000L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK                                          0x80000000L
//RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE
#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT                                       0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT                                   0x8
#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK                                         0x00000001L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK                                     0x00000100L
//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT                              0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT                          0x1
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT                        0x2
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT                            0x3
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT                              0x4
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT                             0x5
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT                       0x6
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT                0x7
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK                                0x00000001L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK                            0x00000002L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK                          0x00000004L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK                              0x00000008L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK                                0x00000010L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK                               0x00000020L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK                         0x00000040L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK                  0x00000080L
//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT                                   0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK                                     0xFFFFFFFFL
//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT                                   0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK                                     0xFFFFFFFFL
//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT                                   0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK                                     0xFFFFFFFFL
//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT                                   0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK                                     0xFFFFFFFFL
//RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT                                  0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK                                    0xFFFFFFFFL
//RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL
#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT                                     0x0
#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT                              0x3
#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK                                       0x00000007L
#define RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK                                0x00000008L


// addressBlock: nbio_nbif_bif_rst_bif_rst_regblk
//HARD_RST_CTRL
#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT                                                                 0x0
#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT                                                          0x1
#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT                                                                 0x2
#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT                                                          0x3
#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT                                                                   0x4
#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT                                                            0x5
#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT                                                                   0x6
#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT                                                            0x7
#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT                                                              0x1c
#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT                                                              0x1d
#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT                                                                 0x1e
#define HARD_RST_CTRL__CORE_RST_EN__SHIFT                                                                     0x1f
#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK                                                                   0x00000001L
#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK                                                            0x00000002L
#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK                                                                   0x00000004L
#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK                                                            0x00000008L
#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK                                                                     0x00000010L
#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK                                                              0x00000020L
#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK                                                                     0x00000040L
#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK                                                              0x00000080L
#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK                                                                0x10000000L
#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK                                                                0x20000000L
#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK                                                                   0x40000000L
#define HARD_RST_CTRL__CORE_RST_EN_MASK                                                                       0x80000000L
//RSMU_SOFT_RST_CTRL
#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT                                                            0x0
#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT                                                     0x1
#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT                                                            0x2
#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT                                                     0x3
#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT                                                              0x4
#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT                                                       0x5
#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT                                                              0x6
#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT                                                       0x7
#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT                                                         0x1c
#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT                                                         0x1d
#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT                                                            0x1e
#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT                                                                0x1f
#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK                                                              0x00000001L
#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK                                                       0x00000002L
#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK                                                              0x00000004L
#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK                                                       0x00000008L
#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK                                                                0x00000010L
#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK                                                         0x00000020L
#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK                                                                0x00000040L
#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK                                                         0x00000080L
#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK                                                           0x10000000L
#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK                                                           0x20000000L
#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK                                                              0x40000000L
#define RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK                                                                  0x80000000L
//SELF_SOFT_RST
#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT                                                                   0x0
#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT                                                            0x1
#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT                                                                   0x2
#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT                                                            0x3
#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT                                                                     0x4
#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT                                                              0x5
#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT                                                                     0x6
#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT                                                              0x7
#define SELF_SOFT_RST__HRPU_SDP_PORT_RST__SHIFT                                                               0x18
#define SELF_SOFT_RST__GSID_SDP_PORT_RST__SHIFT                                                               0x19
#define SELF_SOFT_RST__GMIU_SDP_PORT_RST__SHIFT                                                               0x1a
#define SELF_SOFT_RST__GMID_SDP_PORT_RST__SHIFT                                                               0x1b
#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT                                                                 0x1c
#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT                                                                 0x1d
#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT                                                                    0x1e
#define SELF_SOFT_RST__CORE_RST__SHIFT                                                                        0x1f
#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK                                                                     0x00000001L
#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK                                                              0x00000002L
#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK                                                                     0x00000004L
#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK                                                              0x00000008L
#define SELF_SOFT_RST__EP0_CFG_RST_MASK                                                                       0x00000010L
#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK                                                                0x00000020L
#define SELF_SOFT_RST__EP0_PRV_RST_MASK                                                                       0x00000040L
#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK                                                                0x00000080L
#define SELF_SOFT_RST__HRPU_SDP_PORT_RST_MASK                                                                 0x01000000L
#define SELF_SOFT_RST__GSID_SDP_PORT_RST_MASK                                                                 0x02000000L
#define SELF_SOFT_RST__GMIU_SDP_PORT_RST_MASK                                                                 0x04000000L
#define SELF_SOFT_RST__GMID_SDP_PORT_RST_MASK                                                                 0x08000000L
#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK                                                                   0x10000000L
#define SELF_SOFT_RST__CORE_STICKY_RST_MASK                                                                   0x20000000L
#define SELF_SOFT_RST__RELOAD_STRAP_MASK                                                                      0x40000000L
#define SELF_SOFT_RST__CORE_RST_MASK                                                                          0x80000000L
//BIF_GFX_DRV_VPU_RST
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT                                                      0x0
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT                                              0x1
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT                                               0x2
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT                                                      0x3
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT                                               0x4
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT                                                      0x5
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT                                               0x6
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT                                                      0x7
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK                                                        0x00000001L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK                                                0x00000002L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK                                                 0x00000004L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK                                                        0x00000008L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK                                                 0x00000010L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK                                                        0x00000020L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK                                                 0x00000040L
#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK                                                        0x00000080L
//BIF_RST_MISC_CTRL
#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT                                                    0x0
#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT                                                                0x2
#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT                                                            0x4
#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT                                                     0x5
#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT                                                      0x6
#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT                                                     0x8
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT                                                          0x9
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT                                                       0xa
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT                                                           0xd
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT                                                          0xf
#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT                                              0x11
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT                                                       0x17
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT                                                    0x18
#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK                                                      0x00000001L
#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK                                                                  0x0000000CL
#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK                                                              0x00000010L
#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK                                                       0x00000020L
#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK                                                        0x00000040L
#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK                                                       0x00000100L
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK                                                            0x00000200L
#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK                                                         0x00001C00L
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK                                                             0x00006000L
#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK                                                            0x00018000L
#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK                                                0x000E0000L
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK                                                         0x00800000L
#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK                                                      0x03000000L
//BIF_RST_MISC_CTRL2
#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x10
#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x11
#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT                                                   0x12
#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT                                                         0x1f
#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK                                                      0x00010000L
#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK                                                      0x00020000L
#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK                                                     0x00040000L
#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK                                                           0x80000000L
//BIF_RST_MISC_CTRL3
#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT                                                                0x0
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT                                                        0x4
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT                                                           0x6
#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT                                                    0x7
#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT                                                    0xa
#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT                                                    0xd
#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE__SHIFT                                                        0x10
#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK                                                                  0x0000000FL
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK                                                          0x00000030L
#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK                                                             0x00000040L
#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK                                                      0x00000380L
#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK                                                      0x00001C00L
#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK                                                      0x0000E000L
#define BIF_RST_MISC_CTRL3__RSMU_SOFT_RST_CYCLE_MASK                                                          0x00FF0000L
//BIF_RST_GFXVF_FLR_IDLE
#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT                                                         0x0
#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT                                                         0x1
#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT                                                         0x2
#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT                                                         0x3
#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT                                                         0x4
#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT                                                         0x5
#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT                                                         0x6
#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT                                                         0x7
#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT                                                         0x8
#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT                                                         0x9
#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT                                                        0xa
#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT                                                        0xb
#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT                                                        0xc
#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT                                                        0xd
#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT                                                        0xe
#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT                                                        0xf
#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT                                                      0x1f
#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE_MASK                                                           0x00000001L
#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE_MASK                                                           0x00000002L
#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE_MASK                                                           0x00000004L
#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE_MASK                                                           0x00000008L
#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE_MASK                                                           0x00000010L
#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE_MASK                                                           0x00000020L
#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE_MASK                                                           0x00000040L
#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE_MASK                                                           0x00000080L
#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE_MASK                                                           0x00000100L
#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE_MASK                                                           0x00000200L
#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE_MASK                                                          0x00000400L
#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE_MASK                                                          0x00000800L
#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE_MASK                                                          0x00001000L
#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE_MASK                                                          0x00002000L
#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE_MASK                                                          0x00004000L
#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE_MASK                                                          0x00008000L
#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK                                                        0x80000000L
//DEV0_PF0_FLR_RST_CTRL
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT                                                               0x5
#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT                                                        0x6
#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT                                                               0x7
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT                                                          0x8
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT                                                  0x9
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT                                                   0xa
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT                                                          0xb
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT                                                   0xc
#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT                                                            0xd
#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT                                                     0xe
#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT                                                            0xf
#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT                                                            0x10
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT                                                   0x1f
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN_MASK                                                                 0x00000020L
#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN_MASK                                                          0x00000040L
#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN_MASK                                                                 0x00000080L
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK                                                            0x00000100L
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK                                                    0x00000200L
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK                                                     0x00000400L
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK                                                            0x00000800L
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK                                                     0x00001000L
#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN_MASK                                                              0x00002000L
#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN_MASK                                                       0x00004000L
#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN_MASK                                                              0x00008000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK                                                              0x00010000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK                                                     0x80000000L
//DEV0_PF1_FLR_RST_CTRL
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF2_FLR_RST_CTRL
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF3_FLR_RST_CTRL
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF4_FLR_RST_CTRL
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF5_FLR_RST_CTRL
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF6_FLR_RST_CTRL
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//DEV0_PF7_FLR_RST_CTRL
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
//BIF_INST_RESET_INTR_STS
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT                                               0x0
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0x1
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT                                                 0x2
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT                                                 0x3
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT                                                 0x4
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK                                                 0x00000001L
#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000002L
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK                                                   0x00000004L
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK                                                   0x00000008L
#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK                                                   0x00000010L
//BIF_PF_FLR_INTR_STS
#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT                                                     0x0
#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT                                                     0x1
#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT                                                     0x2
#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT                                                     0x3
#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT                                                     0x4
#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT                                                     0x5
#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT                                                     0x6
#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT                                                     0x7
#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK                                                       0x00000001L
#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK                                                       0x00000002L
#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS_MASK                                                       0x00000004L
#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS_MASK                                                       0x00000008L
#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS_MASK                                                       0x00000010L
#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS_MASK                                                       0x00000020L
#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS_MASK                                                       0x00000040L
#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS_MASK                                                       0x00000080L
//BIF_D3HOTD0_INTR_STS
#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x0
#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x1
#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT                                                0x2
#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT                                                0x3
#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT                                                0x4
#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT                                                0x5
#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT                                                0x6
#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT                                                0x7
#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00000001L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00000002L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS_MASK                                                  0x00000004L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS_MASK                                                  0x00000008L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS_MASK                                                  0x00000010L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS_MASK                                                  0x00000020L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS_MASK                                                  0x00000040L
#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS_MASK                                                  0x00000080L
//BIF_POWER_INTR_STS
#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x0
#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT                                                      0x10
#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000001L
#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK                                                        0x00010000L
//BIF_PF_DSTATE_INTR_STS
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT                                               0x0
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT                                               0x1
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT                                               0x2
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT                                               0x3
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT                                               0x4
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT                                               0x5
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT                                               0x6
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT                                               0x7
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK                                                 0x00000001L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK                                                 0x00000002L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK                                                 0x00000004L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK                                                 0x00000008L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK                                                 0x00000010L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK                                                 0x00000020L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK                                                 0x00000040L
#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK                                                 0x00000080L
//BIF_PF0_VF_FLR_INTR_STS
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT                                                  0x0
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT                                                  0x1
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT                                                  0x2
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT                                                  0x3
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT                                                  0x4
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT                                                  0x5
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT                                                  0x6
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT                                                  0x7
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT                                                  0x8
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT                                                  0x9
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT                                                 0xa
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT                                                 0xb
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT                                                 0xc
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT                                                 0xd
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT                                                 0xe
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT                                                 0xf
#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT                                               0x1f
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS_MASK                                                    0x00000001L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS_MASK                                                    0x00000002L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS_MASK                                                    0x00000004L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS_MASK                                                    0x00000008L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS_MASK                                                    0x00000010L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS_MASK                                                    0x00000020L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS_MASK                                                    0x00000040L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS_MASK                                                    0x00000080L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS_MASK                                                    0x00000100L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS_MASK                                                    0x00000200L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS_MASK                                                   0x00000400L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS_MASK                                                   0x00000800L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS_MASK                                                   0x00001000L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS_MASK                                                   0x00002000L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS_MASK                                                   0x00004000L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS_MASK                                                   0x00008000L
#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS_MASK                                                 0x80000000L
//BIF_INST_RESET_INTR_MASK
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT                                             0x0
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0x1
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT                                               0x2
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT                                               0x3
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT                                               0x4
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK                                               0x00000001L
#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000002L
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK                                                 0x00000004L
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK                                                 0x00000008L
#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK                                                 0x00000010L
//BIF_PF_FLR_INTR_MASK
#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT                                                   0x0
#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT                                                   0x1
#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT                                                   0x2
#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT                                                   0x3
#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT                                                   0x4
#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT                                                   0x5
#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT                                                   0x6
#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT                                                   0x7
#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK                                                     0x00000001L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK                                                     0x00000002L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK_MASK                                                     0x00000004L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK_MASK                                                     0x00000008L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK_MASK                                                     0x00000010L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK_MASK                                                     0x00000020L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK_MASK                                                     0x00000040L
#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK_MASK                                                     0x00000080L
//BIF_D3HOTD0_INTR_MASK
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x0
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x1
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT                                              0x2
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT                                              0x3
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT                                              0x4
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT                                              0x5
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT                                              0x6
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT                                              0x7
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00000001L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00000002L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK_MASK                                                0x00000004L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK_MASK                                                0x00000008L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK_MASK                                                0x00000010L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK_MASK                                                0x00000020L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK_MASK                                                0x00000040L
#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK_MASK                                                0x00000080L
//BIF_POWER_INTR_MASK
#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x0
#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT                                                    0x10
#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000001L
#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK                                                      0x00010000L
//BIF_PF_DSTATE_INTR_MASK
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT                                             0x0
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT                                             0x1
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT                                             0x2
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT                                             0x3
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT                                             0x4
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT                                             0x5
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT                                             0x6
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT                                             0x7
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK                                               0x00000001L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK                                               0x00000002L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK                                               0x00000004L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK                                               0x00000008L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK                                               0x00000010L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK                                               0x00000020L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK                                               0x00000040L
#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK                                               0x00000080L
//BIF_PF0_VF_FLR_INTR_MASK
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT                                                0x0
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT                                                0x1
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT                                                0x2
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT                                                0x3
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT                                                0x4
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT                                                0x5
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT                                                0x6
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT                                                0x7
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT                                                0x8
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT                                                0x9
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT                                               0xa
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT                                               0xb
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT                                               0xc
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT                                               0xd
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT                                               0xe
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT                                               0xf
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT                                             0x1f
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK_MASK                                                  0x00000001L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK_MASK                                                  0x00000002L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK_MASK                                                  0x00000004L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK_MASK                                                  0x00000008L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK_MASK                                                  0x00000010L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK_MASK                                                  0x00000020L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK_MASK                                                  0x00000040L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK_MASK                                                  0x00000080L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK_MASK                                                  0x00000100L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK_MASK                                                  0x00000200L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK_MASK                                                 0x00000400L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK_MASK                                                 0x00000800L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK_MASK                                                 0x00001000L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK_MASK                                                 0x00002000L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK_MASK                                                 0x00004000L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK_MASK                                                 0x00008000L
#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK_MASK                                               0x80000000L
//BIF_PF_FLR_RST
#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                               0x0
#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                               0x1
#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT                                                               0x2
#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT                                                               0x3
#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT                                                               0x4
#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT                                                               0x5
#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT                                                               0x6
#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT                                                               0x7
#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                 0x00000001L
#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                 0x00000002L
#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST_MASK                                                                 0x00000004L
#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST_MASK                                                                 0x00000008L
#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST_MASK                                                                 0x00000010L
#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST_MASK                                                                 0x00000020L
#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST_MASK                                                                 0x00000040L
#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST_MASK                                                                 0x00000080L
//BIF_PF0_VF_FLR_RST
#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT                                                            0x0
#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT                                                            0x1
#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT                                                            0x2
#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT                                                            0x3
#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT                                                            0x4
#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT                                                            0x5
#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT                                                            0x6
#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT                                                            0x7
#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT                                                            0x8
#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT                                                            0x9
#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT                                                           0xa
#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT                                                           0xb
#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT                                                           0xc
#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT                                                           0xd
#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT                                                           0xe
#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT                                                           0xf
#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT                                                         0x1f
#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST_MASK                                                              0x00000001L
#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST_MASK                                                              0x00000002L
#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST_MASK                                                              0x00000004L
#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST_MASK                                                              0x00000008L
#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST_MASK                                                              0x00000010L
#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST_MASK                                                              0x00000020L
#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST_MASK                                                              0x00000040L
#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST_MASK                                                              0x00000080L
#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST_MASK                                                              0x00000100L
#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST_MASK                                                              0x00000200L
#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST_MASK                                                             0x00000400L
#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST_MASK                                                             0x00000800L
#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST_MASK                                                             0x00001000L
#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST_MASK                                                             0x00002000L
#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST_MASK                                                             0x00004000L
#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST_MASK                                                             0x00008000L
#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST_MASK                                                           0x80000000L
//BIF_DEV0_PF0_DSTATE_VALUE
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF1_DSTATE_VALUE
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF2_DSTATE_VALUE
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF3_DSTATE_VALUE
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF4_DSTATE_VALUE
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF5_DSTATE_VALUE
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF6_DSTATE_VALUE
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//BIF_DEV0_PF7_DSTATE_VALUE
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT                                           0x0
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT                                           0x10
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE_MASK                                             0x00000003L
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE_MASK                                             0x00030000L
//DEV0_PF0_D3HOTD0_RST_CTRL
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF1_D3HOTD0_RST_CTRL
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF2_D3HOTD0_RST_CTRL
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF3_D3HOTD0_RST_CTRL
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF4_D3HOTD0_RST_CTRL
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF5_D3HOTD0_RST_CTRL
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF6_D3HOTD0_RST_CTRL
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//DEV0_PF7_D3HOTD0_RST_CTRL
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
//BIF_PORT0_DSTATE_VALUE
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT                                                 0x0
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT                                                 0x10
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK                                                   0x00030000L


// addressBlock: nbio_nbif_bif_ras_bif_ras_regblk
//BIF_RAS_LEAF0_CTRL
#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//BIF_RAS_LEAF1_CTRL
#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//BIF_RAS_LEAF2_CTRL
#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT                                                              0x0
#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT                                                         0x1
#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT                                                            0x2
#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT                                                              0x4
#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT                                                         0x5
#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT                                                            0x6
#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT                                                             0x10
#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT                                                              0x11
#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT                                                             0x12
#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT                                                             0x13
#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT                                                             0x14
#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT                                                             0x15
#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN_MASK                                                                0x00000001L
#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK                                                           0x00000002L
#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK                                                              0x00000004L
#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN_MASK                                                                0x00000010L
#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK                                                           0x00000020L
#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK                                                              0x00000040L
#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV_MASK                                                               0x00010000L
#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV_MASK                                                                0x00020000L
#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET_MASK                                                               0x00040000L
#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET_MASK                                                               0x00080000L
#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT_MASK                                                               0x00100000L
#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED_MASK                                                               0x00200000L
//BIF_RAS_MISC_CTRL
#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT                                                    0x0
#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN_MASK                                                      0x00000001L
//BIF_IOHUB_RAS_IH_CNTL
#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT                                                          0x0
#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN_MASK                                                            0x00000001L
//BIF_RAS_VWR_FROM_IOHUB
#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT                                                       0x0
#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG_MASK                                                         0x00000001L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_1_COMMAND
#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF0_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF0_1_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF0_1_STATUS
#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_1_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF0_1_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF0_1_STATUS__PCI_66_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV0_EPF0_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF0_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF0_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF0_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF0_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_1_LATENCY
#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF0_1_HEADER
#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF0_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_1_BIST
#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF0_1_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_1_CAP_PTR__CAP_PTR_MASK                                                             0x000000FFL
//BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF0_1_MIN_GRANT
#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF0_1_MAX_LATENCY
#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF0_1_PMI_CAP
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF0_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF0_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
//BIF_CFG_DEV0_EPF0_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF0_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
//BIF_CFG_DEV0_EPF0_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
//BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RESERVED__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF0_1_LINK_CAP2__RESERVED_MASK                                                          0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF0_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                  0x4
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                    0x0010L
#define BIF_CFG_DEV0_EPF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                      0x0020L
//BIF_CFG_DEV0_EPF0_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_1_SLOT_CAP2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_1_SLOT_CAP2__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_SLOT_CNTL2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_SLOT_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0x0000FFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0x0000FFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF0_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
//BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x1FL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3__RESERVED_MASK                                                    0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                             0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
//BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
//BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0x00FFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK     0x00000007L
#define BIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x00000001L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x00000002L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK                       0x000000FFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK                       0x0000FF00L
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
//BIF_CFG_DEV0_EPF1_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_1_COMMAND
#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING__SHIFT                                                       0x7
#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN__SHIFT                                                           0x8
#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS__SHIFT                                                           0xa
#define BIF_CFG_DEV0_EPF1_1_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__AD_STEPPING_MASK                                                         0x0080L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__SERR_EN_MASK                                                             0x0100L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
#define BIF_CFG_DEV0_EPF1_1_COMMAND__INT_DIS_MASK                                                             0x0400L
//BIF_CFG_DEV0_EPF1_1_STATUS
#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST__SHIFT                                                           0x4
#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN__SHIFT                                                          0x5
#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF1_1_STATUS__INT_STATUS_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF1_1_STATUS__CAP_LIST_MASK                                                             0x0010L
#define BIF_CFG_DEV0_EPF1_1_STATUS__PCI_66_EN_MASK                                                            0x0020L
#define BIF_CFG_DEV0_EPF1_1_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF1_1_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
#define BIF_CFG_DEV0_EPF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
#define BIF_CFG_DEV0_EPF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF1_1_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF1_1_REVISION_ID
#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
#define BIF_CFG_DEV0_EPF1_1_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
//BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF1_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF1_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF1_1_LATENCY
#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
//BIF_CFG_DEV0_EPF1_1_HEADER
#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF1_1_HEADER__HEADER_TYPE_MASK                                                          0x7FL
#define BIF_CFG_DEV0_EPF1_1_HEADER__DEVICE_TYPE_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF1_1_BIST
#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP__SHIFT                                                            0x0
#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT__SHIFT                                                            0x6
#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP__SHIFT                                                             0x7
#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_COMP_MASK                                                              0x0FL
#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_STRT_MASK                                                              0x40L
#define BIF_CFG_DEV0_EPF1_1_BIST__BIST_CAP_MASK                                                               0x80L
//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_CAP_PTR
#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_1_CAP_PTR__CAP_PTR_MASK                                                             0x000000FFL
//BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
//BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
//BIF_CFG_DEV0_EPF1_1_MIN_GRANT
#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_1_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
//BIF_CFG_DEV0_EPF1_1_MAX_LATENCY
#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
//BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
#define BIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
//BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF1_1_PMI_CAP
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION__SHIFT                                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__VERSION_MASK                                                             0x0007L
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
#define BIF_CFG_DEV0_EPF1_1_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
//BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
#define BIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF1_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION__SHIFT                                                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__VERSION_MASK                                                            0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
//BIF_CFG_DEV0_EPF1_1_LINK_CAP
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
//BIF_CFG_DEV0_EPF1_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
//BIF_CFG_DEV0_EPF1_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
//BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
//BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
#define BIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
//BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF1_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED__SHIFT                                                        0x9
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
#define BIF_CFG_DEV0_EPF1_1_LINK_CAP2__RESERVED_MASK                                                          0xFFFFFE00L
//BIF_CFG_DEV0_EPF1_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
#define BIF_CFG_DEV0_EPF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
//BIF_CFG_DEV0_EPF1_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                                  0x4
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                          0x0002L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                    0x0010L
#define BIF_CFG_DEV0_EPF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                      0x0020L
//BIF_CFG_DEV0_EPF1_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF1_1_SLOT_CAP2__RESERVED_MASK                                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_SLOT_CNTL2__RESERVED_MASK                                                         0xFFFFL
//BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_SLOT_STATUS2__RESERVED_MASK                                                       0xFFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
#define BIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
//BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
//BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA__MSI_DATA_MASK                                                       0x0000FFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_MASK
#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0x0000FFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
#define BIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
//BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
#define BIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
//BIF_CFG_DEV0_EPF1_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
#define BIF_CFG_DEV0_EPF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
//BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
//BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0x00FFFFF0L
//BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x0007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x00E0L
#define BIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x1FL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3
#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED__SHIFT                                                  0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3__RESERVED_MASK                                                    0xFFFFFFFCL
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS__RESERVED_MASK                                             0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT              0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT                0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                     0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK                0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                       0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                  0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED_MASK                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT             0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT                    0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT               0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET_MASK                    0x000FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT_MASK               0x0070L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET_MASK                      0x0F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT_MASK                 0x7000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED_MASK                                     0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
//BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
//BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
//BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC
#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
//BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT                         0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT                        0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED_MASK                             0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED_MASK                           0x00000002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED_MASK                           0x00000004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED_MASK                          0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION_MASK                                0x00000600L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE_MASK                                    0x07FF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL_MASK                                     0x00000007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL__TPH_REQR_EN_MASK                                              0x00000300L
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT                                            0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_MAX_GROUP_MASK                                                    0x003FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_WIN_SIZE_REQ_MASK                                                 0x3F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP__MC_ECRC_REGEN_SUPP_MASK                                              0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE__SHIFT                                                    0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_NUM_GROUP_MASK                                                   0x003FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL__MC_ENABLE_MASK                                                      0x8000L
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT                                              0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_INDEX_POS_MASK                                                  0x0000003FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0__MC_BASE_ADDR_0_MASK                                                0xFFFFF000L
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1__MC_BASE_ADDR_1_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0__MC_RECEIVE_0_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1__MC_RECEIVE_1_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1_MASK                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
//BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0x00FFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF_MASK     0x00000007L
#define BIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT     0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT      0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT     0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT     0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN_MASK        0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN_MASK       0x00000004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN_MASK        0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN_MASK       0x00000400L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN_MASK        0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN_MASK       0x00040000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS_MASK    0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS_MASK    0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS_MASK   0x00000400L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS_MASK    0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS_MASK   0x00040000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x00000001L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x00000002L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT                    0xa
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE_MASK                        0x0000007FL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET_MASK                      0xFFFFFC00L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT                     0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT                     0x8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT                     0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET_MASK                       0x000000FFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET_MASK                       0x0000FF00L
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET_MASK                       0x00FF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT                        0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT                      0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE_MASK                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET_MASK                        0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT                      0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT                    0x10
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE_MASK                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET_MASK                      0xFFFF0000L
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8__DW8_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7_MASK                              0xFFFFFFFFL
//BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8__SHIFT                            0x0
#define BIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8__DW8_MASK                              0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF0_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF0_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF0_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF0_1_BIST
#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF0_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF1_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF1_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF1_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF1_1_BIST
#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF1_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF2_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF2_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF2_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF2_1_BIST
#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF2_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF3_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF3_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF3_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF3_1_BIST
#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF3_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF4_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF4_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF4_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF4_1_BIST
#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF4_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF5_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF5_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF5_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF5_1_BIST
#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF5_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF6_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF6_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF6_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF6_1_BIST
#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF6_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF7_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF7_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF7_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF7_1_BIST
#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF7_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF8_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF8_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF8_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF8_1_BIST
#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF8_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID__VENDOR_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID__DEVICE_ID_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                 0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN__SHIFT                                                 0x2
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                       0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                  0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                         0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN__SHIFT                                                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS__SHIFT                                                       0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__IO_ACCESS_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_ACCESS_EN_MASK                                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__BUS_MASTER_EN_MASK                                                   0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PAL_SNOOP_EN_MASK                                                    0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                           0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__AD_STEPPING_MASK                                                     0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__SERR_EN_MASK                                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__FAST_B2B_EN_MASK                                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_1_COMMAND__INT_DIS_MASK                                                         0x0400L
//BIF_CFG_DEV0_EPF0_VF9_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS__SHIFT                                                     0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST__SHIFT                                                       0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_EN__SHIFT                                                      0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                          0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                          0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                          0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__INT_STATUS_MASK                                                       0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__CAP_LIST_MASK                                                         0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PCI_66_EN_MASK                                                        0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__FAST_BACK_CAPABLE_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__DEVSEL_TIMING_MASK                                                    0x0600L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                            0x1000L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                            0x2000L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF9_1_STATUS__PARITY_ERROR_DETECTED_MASK                                            0x8000L
//BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                              0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MINOR_REV_ID_MASK                                                0x0FL
#define BIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID__MAJOR_REV_ID_MASK                                                0xF0L
//BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS__SUB_CLASS_MASK                                                     0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS__BASE_CLASS_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                              0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_LATENCY__LATENCY_TIMER_MASK                                                   0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE__SHIFT                                                    0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__HEADER_TYPE_MASK                                                      0x7FL
#define BIF_CFG_DEV0_EPF0_VF9_1_HEADER__DEVICE_TYPE_MASK                                                      0x80L
//BIF_CFG_DEV0_EPF0_VF9_1_BIST
#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP__SHIFT                                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT__SHIFT                                                        0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP__SHIFT                                                         0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_COMP_MASK                                                          0x0FL
#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_STRT_MASK                                                          0x40L
#define BIF_CFG_DEV0_EPF0_VF9_1_BIST__BIST_CAP_MASK                                                           0x80L
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6__BASE_ADDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                               0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                          0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                 0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR__CAP_PTR_MASK                                                         0x000000FFL
//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                           0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                             0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                              0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__VERSION_MASK                                                        0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__DEVICE_TYPE_MASK                                                    0x00F0L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                               0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                0x3E00L
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                               0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                      0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                   0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                  0x12
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                  0x1a
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                0x1c
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                          0x00000007L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                 0x00000018L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                 0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                       0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                        0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                     0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                    0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                    0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                  0x10000000L
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                          0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                           0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                           0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                           0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                               0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                              0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                            0x00E0L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                             0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                             0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                             0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                 0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                       0x7000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL__INITIATE_FLR_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                               0x2
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__CORR_ERR_MASK                                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                             0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__FATAL_ERR_MASK                                                 0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__USR_DETECTED_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__AUX_PWR_MASK                                                   0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                         0x0020L
//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                             0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                       0x12
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                  0x13
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                     0x15
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER__SHIFT                                                  0x18
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_SPEED_MASK                                                     0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_WIDTH_MASK                                                     0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PM_SUPPORT_MASK                                                     0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                               0x00007000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                0x00038000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                         0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                    0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                    0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                       0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                    0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP__PORT_NUMBER_MASK                                                    0xFF000000L
//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS__SHIFT                                                    0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                            0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                 0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                   0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                   0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__PM_CONTROL_MASK                                                    0x0003L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_DIS_MASK                                                      0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__RETRAIN_LINK_MASK                                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                              0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                     0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                   0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                     0x0800L
//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                       0x03F0L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_TRAINING_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                              0x1000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__DL_ACTIVE_MASK                                                   0x2000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                   0x4000L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                 0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                        0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                            0x12
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                  0x16
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                 0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                  0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                  0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                  0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                      0x00000200L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                   0x00000400L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                               0x00000800L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                          0x00003000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                              0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                    0x00C00000L
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                        0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                    0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                   0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                  0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                          0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                          0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                   0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                         0x0100L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                      0x0200L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__LTR_EN_MASK                                                     0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__OBFF_EN_MASK                                                    0x6000L
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                0x8000L
//BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2__RESERVED_MASK                                                 0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                        0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                         0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RESERVED__SHIFT                                                    0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                          0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                           0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2__RESERVED_MASK                                                      0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                       0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                             0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                      0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                            0x000FL
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                  0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                        0x0040L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                  0x0380L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                         0x0400L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                               0x0800L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                        0xF000L
//BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                    0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                              0x2
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                              0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                              0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                                0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                       0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                      0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                                0x0008L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                                0x0010L
#define BIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                  0x0020L
//BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2__RESERVED__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2__RESERVED_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2__RESERVED_MASK                                                     0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2__RESERVED__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2__RESERVED_MASK                                                   0xFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                 0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__CAP_ID_MASK                                                     0x00FFL
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                   0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                            0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_EN_MASK                                                     0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                              0x000EL
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                               0x0070L
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                  0x0100L
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                       0x2
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                         0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA__MSI_DATA_MASK                                                   0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK__MSI_MASK_MASK                                                       0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                             0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64__MSI_MASK_64_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING__MSI_PENDING_MASK                                                 0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                          0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                 0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                           0x07FFL
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                            0x4000L
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                   0x8000L
//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                               0x00000007L
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                            0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                   0x00000007L
#define BIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                             0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                            0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                               0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                              0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                     0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                  0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                        0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                       0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                    0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                           0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                 0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                              0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                 0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                  0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                           0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                               0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                0x11
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                0x13
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                          0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                           0x15
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                          0x16
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                          0x17
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                 0x18
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                  0x19
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                   0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                   0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                    0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                             0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                 0x00010000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                  0x00020000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                   0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                  0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                            0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                             0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                            0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                            0x00800000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                   0x01000000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                    0x02000000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                  0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                      0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                               0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                   0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                    0x11
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                     0x12
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                    0x13
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                              0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                               0x15
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                              0x16
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                              0x17
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                     0x18
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                      0x19
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                       0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                    0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                        0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                 0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                     0x00010000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                      0x00020000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                       0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                      0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                 0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                0x00800000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                       0x01000000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                        0x02000000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                          0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                             0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                              0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                         0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                       0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                           0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                            0x11
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                             0x12
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                            0x13
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                      0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                       0x15
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                      0x16
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                      0x17
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x18
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT              0x19
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                               0x00000010L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                            0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                               0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                           0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                         0x00008000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                             0x00010000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                              0x00020000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                               0x00040000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                              0x00080000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                        0x00100000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                         0x00200000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                        0x00400000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                        0x00800000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK               0x01000000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                0x02000000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                   0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                       0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                      0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                     0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                              0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                     0x00000001L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                     0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                         0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                        0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                0x00008000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                       0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                      0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                           0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                          0xc
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                         0xd
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                  0xe
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                         0x00000001L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                         0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                        0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                             0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                            0x00001000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                           0x00002000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                    0x00004000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                    0x00008000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                   0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                  0x7
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                   0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                              0x9
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                               0xa
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                          0xb
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                     0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                      0x00000020L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                       0x00000040L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                    0x00000080L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                     0x00000100L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                0x00000200L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                 0x00000400L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                            0x00000800L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                   0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                         0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                     0x5
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                              0x6
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                         0x001FL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                0x0040L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                              0xf
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__STU_MASK                                                       0x001FL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                0x8000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                          0xFF00L
//BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                  0x1
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                    0x0002L
#define BIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                        0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_1_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF10_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF10_1_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF10_1_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF10_1_BIST
#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF10_1_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_1_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF11_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF11_1_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF11_1_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF11_1_BIST
#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF11_1_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_1_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF12_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF12_1_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF12_1_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF12_1_BIST
#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF12_1_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_1_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF13_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF13_1_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF13_1_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF13_1_BIST
#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF13_1_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_1_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF14_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF14_1_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF14_1_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF14_1_BIST
#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF14_1_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
//BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID
#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID__VENDOR_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID__DEVICE_ID_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_COMMAND
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN__SHIFT                                                0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN__SHIFT                                                0x2
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                      0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN__SHIFT                                                 0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                        0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING__SHIFT                                                  0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN__SHIFT                                                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN__SHIFT                                                  0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS__SHIFT                                                      0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__IO_ACCESS_EN_MASK                                                   0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_ACCESS_EN_MASK                                                  0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__BUS_MASTER_EN_MASK                                                  0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SPECIAL_CYCLE_EN_MASK                                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PAL_SNOOP_EN_MASK                                                   0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                          0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__AD_STEPPING_MASK                                                    0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__SERR_EN_MASK                                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__FAST_B2B_EN_MASK                                                    0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_1_COMMAND__INT_DIS_MASK                                                        0x0400L
//BIF_CFG_DEV0_EPF0_VF15_1_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS__SHIFT                                                    0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST__SHIFT                                                      0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_EN__SHIFT                                                     0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE__SHIFT                                             0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING__SHIFT                                                 0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                           0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                         0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                         0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                         0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__INT_STATUS_MASK                                                      0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__CAP_LIST_MASK                                                        0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PCI_66_EN_MASK                                                       0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__FAST_BACK_CAPABLE_MASK                                               0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__DEVSEL_TIMING_MASK                                                   0x0600L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNAL_TARGET_ABORT_MASK                                             0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_TARGET_ABORT_MASK                                           0x1000L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__RECEIVED_MASTER_ABORT_MASK                                           0x2000L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF15_1_STATUS__PARITY_ERROR_DETECTED_MASK                                           0x8000L
//BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID
#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID__SHIFT                                             0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID__SHIFT                                             0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MINOR_REV_ID_MASK                                               0x0FL
#define BIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID__MAJOR_REV_ID_MASK                                               0xF0L
//BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE
#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE__PROG_INTERFACE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS
#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS__SUB_CLASS_MASK                                                    0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS__BASE_CLASS_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE
#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                           0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                             0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_LATENCY
#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_LATENCY__LATENCY_TIMER_MASK                                                  0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_HEADER
#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE__SHIFT                                                   0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__HEADER_TYPE_MASK                                                     0x7FL
#define BIF_CFG_DEV0_EPF0_VF15_1_HEADER__DEVICE_TYPE_MASK                                                     0x80L
//BIF_CFG_DEV0_EPF0_VF15_1_BIST
#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP__SHIFT                                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT__SHIFT                                                       0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP__SHIFT                                                        0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_COMP_MASK                                                         0x0FL
#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_STRT_MASK                                                         0x40L
#define BIF_CFG_DEV0_EPF0_VF15_1_BIST__BIST_CAP_MASK                                                          0x80L
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6__BASE_ADDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID
#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                              0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                         0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                0xFFFF0000L
//BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR
#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR
#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR__SHIFT                                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR__CAP_PTR_MASK                                                        0x000000FFL
//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE
#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                          0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN
#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                            0xFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION__SHIFT                                                     0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                 0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                            0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                             0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__VERSION_MASK                                                       0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__DEVICE_TYPE_MASK                                                   0x00F0L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                              0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                               0x3E00L
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                              0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                              0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                     0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                  0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                 0x12
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                 0x1a
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                               0x1c
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                         0x00000007L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                0x00000018L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__EXTENDED_TAG_MASK                                                0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                      0x000001C0L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                       0x00000E00L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                    0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                   0x03FC0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                   0x0C000000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP__FLR_CAPABLE_MASK                                                 0x10000000L
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                         0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                             0x2
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                            0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                           0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                         0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                          0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                          0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                          0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                              0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                           0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__USR_REPORT_EN_MASK                                              0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                             0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                           0x00E0L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                            0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                            0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                            0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                      0x7000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL__INITIATE_FLR_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR__SHIFT                                               0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                          0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR__SHIFT                                              0x2
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED__SHIFT                                           0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR__SHIFT                                                0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                      0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__CORR_ERR_MASK                                                 0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                            0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__FATAL_ERR_MASK                                                0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__USR_DETECTED_MASK                                             0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__AUX_PWR_MASK                                                  0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                        0x0020L
//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH__SHIFT                                                  0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                            0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                      0x12
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                 0x13
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                    0x15
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER__SHIFT                                                 0x18
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_SPEED_MASK                                                    0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_WIDTH_MASK                                                    0x000003F0L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PM_SUPPORT_MASK                                                    0x00000C00L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                              0x00007000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__L1_EXIT_LATENCY_MASK                                               0x00038000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                        0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                   0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                   0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                      0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                   0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP__PORT_NUMBER_MASK                                                   0xFF000000L
//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                          0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS__SHIFT                                                   0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK__SHIFT                                               0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                           0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                              0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                  0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                  0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__PM_CONTROL_MASK                                                   0x0003L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                            0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_DIS_MASK                                                     0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__RETRAIN_LINK_MASK                                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                             0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__EXTENDED_SYNC_MASK                                                0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                    0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                  0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                    0x0800L
//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                           0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE__SHIFT                                                0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                      0x03F0L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_TRAINING_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                             0x1000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__DL_ACTIVE_MASK                                                  0x2000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                  0x4000L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                               0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                               0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                       0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                           0x12
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                             0x15
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                 0x16
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                0x0000000FL
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                 0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                 0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                 0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                     0x00000200L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                  0x00000400L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                              0x00000800L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                         0x00003000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                             0x000C0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                               0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                   0x00C00000L
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                       0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                         0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                       0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                   0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN__SHIFT                                                  0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                 0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                         0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                           0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                         0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                  0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                        0x0100L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                     0x0200L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__LTR_EN_MASK                                                    0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__OBFF_EN_MASK                                                   0x6000L
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                               0x8000L
//BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2__RESERVED_MASK                                                0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                       0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                        0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RESERVED__SHIFT                                                   0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                         0x000000FEL
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                          0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2__RESERVED_MASK                                                     0xFFFFFE00L
//BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                          0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                     0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                      0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                            0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                     0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                           0x000FL
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                            0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                 0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                       0x0040L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__XMIT_MARGIN_MASK                                                 0x0380L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                        0x0400L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                              0x0800L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                       0xF000L
//BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                    0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT                                   0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT                             0x2
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT                             0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT                             0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT                               0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                      0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_COMPLETE_MASK                                     0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_MASK                               0x0004L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_MASK                               0x0008L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_MASK                               0x0010L
#define BIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_MASK                                 0x0020L
//BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2
#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2__RESERVED__SHIFT                                                   0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2__RESERVED_MASK                                                     0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2
#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2__RESERVED__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2__RESERVED_MASK                                                    0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2
#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2__RESERVED__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2__RESERVED_MASK                                                  0xFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__CAP_ID_MASK                                                    0x00FFL
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST__NEXT_PTR_MASK                                                  0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                           0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                            0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                               0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_EN_MASK                                                    0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                             0x000EL
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                              0x0070L
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                 0x0080L
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                 0x0100L
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                      0x2
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                        0xFFFFFFFCL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA__MSI_DATA_MASK                                                  0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK__MSI_MASK_MASK                                                      0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                          0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                            0x0000FFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64__MSI_MASK_64_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING__SHIFT                                              0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING__MSI_PENDING_MASK                                                0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64__MSI_PENDING_64_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                               0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__CAP_ID_MASK                                                   0x00FFL
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                 0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                         0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                          0x07FFL
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                           0x4000L
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                  0x8000L
//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                            0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                         0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                              0x00000007L
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                           0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                             0x3
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                  0x00000007L
#define BIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                               0xFFFFFFF8L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                             0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                            0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                           0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                               0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                              0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                             0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                     0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                    0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                 0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                       0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                      0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                   0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                        0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                          0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                 0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                               0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                   0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                  0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                 0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                             0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                 0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                            0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                          0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                              0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                               0x11
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                0x12
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                               0x13
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                         0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                          0x15
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                         0x16
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                         0x17
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                0x18
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                 0x19
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                  0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                               0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                  0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                   0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                              0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                            0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                0x00010000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                 0x00020000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                  0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                 0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                           0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                            0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                           0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                           0x00800000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                  0x01000000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                   0x02000000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                    0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                 0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                    0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                     0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                              0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                  0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                   0x11
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                    0x12
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                   0x13
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                             0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                              0x15
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                             0x16
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                             0x17
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                    0x18
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                     0x19
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                      0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                   0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                      0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                       0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                  0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                    0x00010000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                     0x00020000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                      0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                     0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                               0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                               0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                               0x00800000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                      0x01000000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                       0x02000000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                            0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                         0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                            0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                             0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                        0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                      0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                          0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                           0x11
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                            0x12
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                           0x13
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                     0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                      0x15
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                     0x16
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                     0x17
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT            0x18
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT             0x19
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                              0x00000010L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                           0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                              0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                               0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                          0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                        0x00008000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                            0x00010000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                             0x00020000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                              0x00040000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                             0x00080000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                       0x00100000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                        0x00200000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                       0x00400000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                       0x00800000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK              0x01000000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK               0x02000000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                  0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                      0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                     0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                    0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                             0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                    0x00000001L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                    0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                        0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                       0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                      0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                               0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                               0x00008000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                      0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                     0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                          0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                         0xc
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                        0xd
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                 0xe
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                 0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                        0x00000001L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                        0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                       0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                            0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                           0x00001000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                          0x00002000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                   0x00004000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                   0x00008000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                  0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                   0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                    0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                 0x7
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                  0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                             0x9
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                              0xa
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                         0xb
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                    0x0000001FL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                     0x00000020L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                      0x00000040L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                   0x00000080L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                    0x00000100L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                               0x00000200L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                0x00000400L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                           0x00000800L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                  0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                        0xFFFFFFFFL
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                      0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                    0x5
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                             0x6
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                        0x001FL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                      0x0020L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                               0x0040L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU__SHIFT                                                    0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                             0xf
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__STU_MASK                                                      0x001FL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                               0x8000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                       0x8
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                         0xFF00L
//BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                0x0
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                 0x1
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                     0x4
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                  0x0001L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                   0x0002L
#define BIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                       0x0070L


// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXTDEC
//PCIEMSIX_VECT0_ADDR_LO
#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT0_ADDR_HI
#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT0_MSG_DATA
#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT0_CONTROL
#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT1_ADDR_LO
#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT1_ADDR_HI
#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT1_MSG_DATA
#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT1_CONTROL
#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT2_ADDR_LO
#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT2_ADDR_HI
#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT2_MSG_DATA
#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT2_CONTROL
#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT3_ADDR_LO
#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT3_ADDR_HI
#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT3_MSG_DATA
#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT3_CONTROL
#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT4_ADDR_LO
#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT4_ADDR_HI
#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT4_MSG_DATA
#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT4_CONTROL
#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT5_ADDR_LO
#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT5_ADDR_HI
#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT5_MSG_DATA
#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT5_CONTROL
#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT6_ADDR_LO
#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT6_ADDR_HI
#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT6_MSG_DATA
#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT6_CONTROL
#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT7_ADDR_LO
#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT7_ADDR_HI
#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT7_MSG_DATA
#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT7_CONTROL
#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT8_ADDR_LO
#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT8_ADDR_HI
#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT8_MSG_DATA
#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT8_CONTROL
#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT9_ADDR_LO
#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT                                                            0x2
#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO_MASK                                                              0xFFFFFFFCL
//PCIEMSIX_VECT9_ADDR_HI
#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT                                                            0x0
#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI_MASK                                                              0xFFFFFFFFL
//PCIEMSIX_VECT9_MSG_DATA
#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT                                                              0x0
#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA_MASK                                                                0xFFFFFFFFL
//PCIEMSIX_VECT9_CONTROL
#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT                                                               0x0
#define PCIEMSIX_VECT9_CONTROL__MASK_BIT_MASK                                                                 0x00000001L
//PCIEMSIX_VECT10_ADDR_LO
#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT10_ADDR_HI
#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT10_MSG_DATA
#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT10_CONTROL
#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT10_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT11_ADDR_LO
#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT11_ADDR_HI
#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT11_MSG_DATA
#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT11_CONTROL
#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT11_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT12_ADDR_LO
#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT12_ADDR_HI
#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT12_MSG_DATA
#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT12_CONTROL
#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT12_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT13_ADDR_LO
#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT13_ADDR_HI
#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT13_MSG_DATA
#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT13_CONTROL
#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT13_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT14_ADDR_LO
#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT14_ADDR_HI
#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT14_MSG_DATA
#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT14_CONTROL
#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT14_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT15_ADDR_LO
#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT15_ADDR_HI
#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT15_MSG_DATA
#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT15_CONTROL
#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT15_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT16_ADDR_LO
#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT16_ADDR_HI
#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT16_MSG_DATA
#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT16_CONTROL
#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT16_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT17_ADDR_LO
#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT17_ADDR_HI
#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT17_MSG_DATA
#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT17_CONTROL
#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT17_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT18_ADDR_LO
#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT18_ADDR_HI
#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT18_MSG_DATA
#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT18_CONTROL
#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT18_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT19_ADDR_LO
#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT19_ADDR_HI
#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT19_MSG_DATA
#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT19_CONTROL
#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT19_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT20_ADDR_LO
#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT20_ADDR_HI
#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT20_MSG_DATA
#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT20_CONTROL
#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT20_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT21_ADDR_LO
#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT21_ADDR_HI
#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT21_MSG_DATA
#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT21_CONTROL
#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT21_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT22_ADDR_LO
#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT22_ADDR_HI
#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT22_MSG_DATA
#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT22_CONTROL
#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT22_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT23_ADDR_LO
#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT23_ADDR_HI
#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT23_MSG_DATA
#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT23_CONTROL
#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT23_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT24_ADDR_LO
#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT24_ADDR_HI
#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT24_MSG_DATA
#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT24_CONTROL
#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT24_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT25_ADDR_LO
#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT25_ADDR_HI
#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT25_MSG_DATA
#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT25_CONTROL
#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT25_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT26_ADDR_LO
#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT26_ADDR_HI
#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT26_MSG_DATA
#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT26_CONTROL
#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT26_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT27_ADDR_LO
#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT27_ADDR_HI
#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT27_MSG_DATA
#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT27_CONTROL
#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT27_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT28_ADDR_LO
#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT28_ADDR_HI
#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT28_MSG_DATA
#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT28_CONTROL
#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT28_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT29_ADDR_LO
#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT29_ADDR_HI
#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT29_MSG_DATA
#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT29_CONTROL
#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT29_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT30_ADDR_LO
#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT30_ADDR_HI
#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT30_MSG_DATA
#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT30_CONTROL
#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT30_CONTROL__MASK_BIT_MASK                                                                0x00000001L
//PCIEMSIX_VECT31_ADDR_LO
#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT                                                           0x2
#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO_MASK                                                             0xFFFFFFFCL
//PCIEMSIX_VECT31_ADDR_HI
#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT                                                           0x0
#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI_MASK                                                             0xFFFFFFFFL
//PCIEMSIX_VECT31_MSG_DATA
#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT                                                             0x0
#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA_MASK                                                               0xFFFFFFFFL
//PCIEMSIX_VECT31_CONTROL
#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT                                                              0x0
#define PCIEMSIX_VECT31_CONTROL__MASK_BIT_MASK                                                                0x00000001L


// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXPDEC
//PCIEMSIX_PBA
#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT                                                                0x0
#define PCIEMSIX_PBA__MSIX_PENDING_BITS_MASK                                                                  0xFFFFFFFFL


// addressBlock: nbio_pcie_pswusp0_pciedir_p
//PCIEP_RESERVED
#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                                 0x0
#define PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                                   0xFFFFFFFFL
//PCIEP_SCRATCH
#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT                                                                   0x0
#define PCIEP_SCRATCH__PCIEP_SCRATCH_MASK                                                                     0xFFFFFFFFL
//PCIEP_PORT_CNTL
#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN__SHIFT                                                               0x0
#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE__SHIFT                                                             0x1
#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN__SHIFT                                                                0x2
#define PCIEP_PORT_CNTL__NATIVE_PME_EN__SHIFT                                                                 0x3
#define PCIEP_PORT_CNTL__PWR_FAULT_EN__SHIFT                                                                  0x4
#define PCIEP_PORT_CNTL__PMI_BM_DIS__SHIFT                                                                    0x5
#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S__SHIFT                                               0x8
#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE__SHIFT                                                  0x10
#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE__SHIFT                                                  0x12
#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE__SHIFT                                                   0x18
#define PCIEP_PORT_CNTL__SLV_PORT_REQ_EN_MASK                                                                 0x00000001L
#define PCIEP_PORT_CNTL__CI_SNOOP_OVERRIDE_MASK                                                               0x00000002L
#define PCIEP_PORT_CNTL__HOTPLUG_MSG_EN_MASK                                                                  0x00000004L
#define PCIEP_PORT_CNTL__NATIVE_PME_EN_MASK                                                                   0x00000008L
#define PCIEP_PORT_CNTL__PWR_FAULT_EN_MASK                                                                    0x00000010L
#define PCIEP_PORT_CNTL__PMI_BM_DIS_MASK                                                                      0x00000020L
#define PCIEP_PORT_CNTL__CI_SLV_CPL_STATIC_ALLOC_LIMIT_S_MASK                                                 0x00007F00L
#define PCIEP_PORT_CNTL__CI_MAX_CPL_PAYLOAD_SIZE_MODE_MASK                                                    0x00030000L
#define PCIEP_PORT_CNTL__CI_PRIV_MAX_CPL_PAYLOAD_SIZE_MASK                                                    0x001C0000L
#define PCIEP_PORT_CNTL__CI_SLV_RSP_POISONED_UR_MODE_MASK                                                     0x03000000L
//PCIE_TX_CNTL
#define PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                                  0xa
#define PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                                   0xc
#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS__SHIFT                                                               0xe
#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS__SHIFT                                                                 0xf
#define PCIE_TX_CNTL__TX_CPL_PASS_P__SHIFT                                                                    0x14
#define PCIE_TX_CNTL__TX_NP_PASS_P__SHIFT                                                                     0x15
#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS__SHIFT                                                           0x16
#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS__SHIFT                                                         0x17
#define PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                                    0x18
#define PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                                    0x19
#define PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                                    0x1a
#define PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                                    0x00000C00L
#define PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                                     0x00003000L
#define PCIE_TX_CNTL__TX_PACK_PACKET_DIS_MASK                                                                 0x00004000L
#define PCIE_TX_CNTL__TX_FLUSH_TLP_DIS_MASK                                                                   0x00008000L
#define PCIE_TX_CNTL__TX_CPL_PASS_P_MASK                                                                      0x00100000L
#define PCIE_TX_CNTL__TX_NP_PASS_P_MASK                                                                       0x00200000L
#define PCIE_TX_CNTL__TX_CLEAR_EXTRA_PM_REQS_MASK                                                             0x00400000L
#define PCIE_TX_CNTL__TX_FC_UPDATE_TIMEOUT_DIS_MASK                                                           0x00800000L
#define PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                                      0x01000000L
#define PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                                      0x02000000L
#define PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                                      0x04000000L
//PCIE_TX_REQUESTER_ID
#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                                 0x0
#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                                   0x3
#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                                      0x8
#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                                   0x00000007L
#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                                     0x000000F8L
#define PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                                        0x0000FF00L
//PCIE_TX_VENDOR_SPECIFIC
#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA__SHIFT                                                        0x0
#define PCIE_TX_VENDOR_SPECIFIC__TX_VENDOR_DATA_MASK                                                          0x00FFFFFFL
//PCIE_TX_REQUEST_NUM_CNTL
#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP__SHIFT                                                0x18
#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN__SHIFT                                         0x1e
#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN__SHIFT                                             0x1f
#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_MASK                                                  0x3F000000L
#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_VC1_EN_MASK                                           0x40000000L
#define PCIE_TX_REQUEST_NUM_CNTL__TX_NUM_OUTSTANDING_NP_EN_MASK                                               0x80000000L
//PCIE_TX_SEQ
#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ__SHIFT                                                              0x0
#define PCIE_TX_SEQ__TX_ACKD_SEQ__SHIFT                                                                       0x10
#define PCIE_TX_SEQ__TX_NEXT_TRANSMIT_SEQ_MASK                                                                0x00000FFFL
#define PCIE_TX_SEQ__TX_ACKD_SEQ_MASK                                                                         0x0FFF0000L
//PCIE_TX_REPLAY
#define PCIE_TX_REPLAY__TX_REPLAY_NUM__SHIFT                                                                  0x0
#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE__SHIFT                                                      0xf
#define PCIE_TX_REPLAY__TX_REPLAY_TIMER__SHIFT                                                                0x10
#define PCIE_TX_REPLAY__TX_REPLAY_NUM_MASK                                                                    0x00000007L
#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_OVERWRITE_MASK                                                        0x00008000L
#define PCIE_TX_REPLAY__TX_REPLAY_TIMER_MASK                                                                  0xFFFF0000L
//PCIE_TX_ACK_LATENCY_LIMIT
#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT__SHIFT                                                0x0
#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE__SHIFT                                      0xc
#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_MASK                                                  0x00000FFFL
#define PCIE_TX_ACK_LATENCY_LIMIT__TX_ACK_LATENCY_LIMIT_OVERWRITE_MASK                                        0x00001000L
//PCIE_TX_CREDITS_ADVT_P
#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD__SHIFT                                                     0x0
#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH__SHIFT                                                     0x10
#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PD_MASK                                                       0x00000FFFL
#define PCIE_TX_CREDITS_ADVT_P__TX_CREDITS_ADVT_PH_MASK                                                       0x00FF0000L
//PCIE_TX_CREDITS_ADVT_NP
#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD__SHIFT                                                   0x0
#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH__SHIFT                                                   0x10
#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPD_MASK                                                     0x00000FFFL
#define PCIE_TX_CREDITS_ADVT_NP__TX_CREDITS_ADVT_NPH_MASK                                                     0x00FF0000L
//PCIE_TX_CREDITS_ADVT_CPL
#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD__SHIFT                                                 0x0
#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH__SHIFT                                                 0x10
#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLD_MASK                                                   0x00000FFFL
#define PCIE_TX_CREDITS_ADVT_CPL__TX_CREDITS_ADVT_CPLH_MASK                                                   0x00FF0000L
//PCIE_TX_CREDITS_INIT_P
#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD__SHIFT                                                     0x0
#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH__SHIFT                                                     0x10
#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PD_MASK                                                       0x00000FFFL
#define PCIE_TX_CREDITS_INIT_P__TX_CREDITS_INIT_PH_MASK                                                       0x00FF0000L
//PCIE_TX_CREDITS_INIT_NP
#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD__SHIFT                                                   0x0
#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH__SHIFT                                                   0x10
#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPD_MASK                                                     0x00000FFFL
#define PCIE_TX_CREDITS_INIT_NP__TX_CREDITS_INIT_NPH_MASK                                                     0x00FF0000L
//PCIE_TX_CREDITS_INIT_CPL
#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD__SHIFT                                                 0x0
#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH__SHIFT                                                 0x10
#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLD_MASK                                                   0x00000FFFL
#define PCIE_TX_CREDITS_INIT_CPL__TX_CREDITS_INIT_CPLH_MASK                                                   0x00FF0000L
//PCIE_TX_CREDITS_STATUS
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD__SHIFT                                                      0x0
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH__SHIFT                                                      0x1
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD__SHIFT                                                     0x2
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH__SHIFT                                                     0x3
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD__SHIFT                                                    0x4
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH__SHIFT                                                    0x5
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD__SHIFT                                               0x10
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH__SHIFT                                               0x11
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD__SHIFT                                              0x12
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH__SHIFT                                              0x13
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD__SHIFT                                             0x14
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH__SHIFT                                             0x15
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PD_MASK                                                        0x00000001L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_PH_MASK                                                        0x00000002L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPD_MASK                                                       0x00000004L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_NPH_MASK                                                       0x00000008L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLD_MASK                                                      0x00000010L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_ERR_CPLH_MASK                                                      0x00000020L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PD_MASK                                                 0x00010000L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_PH_MASK                                                 0x00020000L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPD_MASK                                                0x00040000L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_NPH_MASK                                                0x00080000L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLD_MASK                                               0x00100000L
#define PCIE_TX_CREDITS_STATUS__TX_CREDITS_CUR_STATUS_CPLH_MASK                                               0x00200000L
//PCIE_TX_CREDITS_FCU_THRESHOLD
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0__SHIFT                                          0x0
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0__SHIFT                                         0x4
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0__SHIFT                                        0x8
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1__SHIFT                                          0x10
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1__SHIFT                                         0x14
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1__SHIFT                                        0x18
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC0_MASK                                            0x00000007L
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC0_MASK                                           0x00000070L
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC0_MASK                                          0x00000700L
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_P_VC1_MASK                                            0x00070000L
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_NP_VC1_MASK                                           0x00700000L
#define PCIE_TX_CREDITS_FCU_THRESHOLD__TX_FCU_THRESHOLD_CPL_VC1_MASK                                          0x07000000L
//PCIE_P_PORT_LANE_STATUS
#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL__SHIFT                                                    0x0
#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT                                                        0x1
#define PCIE_P_PORT_LANE_STATUS__PORT_LANE_REVERSAL_MASK                                                      0x00000001L
#define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH_MASK                                                          0x0000007EL
//PCIE_FC_P
#define PCIE_FC_P__PD_CREDITS__SHIFT                                                                          0x0
#define PCIE_FC_P__PH_CREDITS__SHIFT                                                                          0x8
#define PCIE_FC_P__PD_CREDITS_MASK                                                                            0x000000FFL
#define PCIE_FC_P__PH_CREDITS_MASK                                                                            0x0000FF00L
//PCIE_FC_NP
#define PCIE_FC_NP__NPD_CREDITS__SHIFT                                                                        0x0
#define PCIE_FC_NP__NPH_CREDITS__SHIFT                                                                        0x8
#define PCIE_FC_NP__NPD_CREDITS_MASK                                                                          0x000000FFL
#define PCIE_FC_NP__NPH_CREDITS_MASK                                                                          0x0000FF00L
//PCIE_FC_CPL
#define PCIE_FC_CPL__CPLD_CREDITS__SHIFT                                                                      0x0
#define PCIE_FC_CPL__CPLH_CREDITS__SHIFT                                                                      0x8
#define PCIE_FC_CPL__CPLD_CREDITS_MASK                                                                        0x000000FFL
#define PCIE_FC_CPL__CPLH_CREDITS_MASK                                                                        0x0000FF00L
//PSWUSP0_PCIE_ERR_CNTL
#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                                       0x0
#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG__SHIFT                                                0x1
#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES__SHIFT                                                   0x2
#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR__SHIFT                                                    0x4
#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR__SHIFT                                                    0x5
#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR__SHIFT                                                    0x6
#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR__SHIFT                                                    0x7
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                                     0x8
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                            0xb
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                            0xc
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                            0xd
#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS__SHIFT                                             0xe
#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS__SHIFT                                            0xf
#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET__SHIFT                                                   0x10
#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                                0x11
#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                                        0x12
#define PSWUSP0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                         0x00000001L
#define PSWUSP0_PCIE_ERR_CNTL__STRAP_FIRST_RCVD_ERR_LOG_MASK                                                  0x00000002L
#define PSWUSP0_PCIE_ERR_CNTL__RX_DROP_ECRC_FAILURES_MASK                                                     0x00000004L
#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_LCRC_ERR_MASK                                                      0x00000010L
#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_LCRC_ERR_MASK                                                      0x00000020L
#define PSWUSP0_PCIE_ERR_CNTL__TX_GENERATE_ECRC_ERR_MASK                                                      0x00000040L
#define PSWUSP0_PCIE_ERR_CNTL__RX_GENERATE_ECRC_ERR_MASK                                                      0x00000080L
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                                       0x00000700L
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                              0x00000800L
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                              0x00001000L
#define PSWUSP0_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                              0x00002000L
#define PSWUSP0_PCIE_ERR_CNTL__CI_P_SLV_BUF_RD_HALT_STATUS_MASK                                               0x00004000L
#define PSWUSP0_PCIE_ERR_CNTL__CI_NP_SLV_BUF_RD_HALT_STATUS_MASK                                              0x00008000L
#define PSWUSP0_PCIE_ERR_CNTL__CI_SLV_BUF_HALT_RESET_MASK                                                     0x00010000L
#define PSWUSP0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                                  0x00020000L
#define PSWUSP0_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                          0x00040000L
//PSWUSP0_PCIE_RX_CNTL
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR__SHIFT                                                         0x0
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR__SHIFT                                                         0x1
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR__SHIFT                                                        0x2
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR__SHIFT                                                        0x3
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR__SHIFT                                                        0x4
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR__SHIFT                                                        0x5
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR__SHIFT                                                         0x6
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR__SHIFT                                               0x7
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                                0x8
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                         0x9
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR__SHIFT                                                         0xa
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR__SHIFT                                                          0xb
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR__SHIFT                                                         0xc
#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL__SHIFT                                                      0xd
#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK__SHIFT                                                           0xe
#define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG__SHIFT                                                      0xf
#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT__SHIFT                                                       0x10
#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE__SHIFT                                                  0x13
#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                                  0x14
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                                0x15
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                                  0x16
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR__SHIFT                                                  0x17
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                               0x18
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                                   0x19
#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                               0x1a
#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                                   0x1b
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_ERR_MASK                                                           0x00000001L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_BE_ERR_MASK                                                           0x00000002L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MSG_ERR_MASK                                                          0x00000004L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CRC_ERR_MASK                                                          0x00000008L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_ERR_MASK                                                          0x00000010L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPL_ERR_MASK                                                          0x00000020L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_EP_ERR_MASK                                                           0x00000040L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_LEN_MISMATCH_ERR_MASK                                                 0x00000080L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                                  0x00000100L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                           0x00000200L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CFG_UR_MASK                                                           0x00000400L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_IO_UR_MASK                                                            0x00000800L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_AT_ERR_MASK                                                           0x00001000L
#define PSWUSP0_PCIE_RX_CNTL__RX_NAK_IF_FIFO_FULL_MASK                                                        0x00002000L
#define PSWUSP0_PCIE_RX_CNTL__RX_GEN_ONE_NAK_MASK                                                             0x00004000L
#define PSWUSP0_PCIE_RX_CNTL__RX_FC_INIT_FROM_REG_MASK                                                        0x00008000L
#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MASK                                                         0x00070000L
#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_CPL_TIMEOUT_MODE_MASK                                                    0x00080000L
#define PSWUSP0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                                    0x00100000L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                                  0x00200000L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                                    0x00400000L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_CPLPREFIX_ERR_MASK                                                    0x00800000L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                                 0x01000000L
#define PSWUSP0_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                                     0x02000000L
#define PSWUSP0_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                                 0x04000000L
#define PSWUSP0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                                     0x08000000L
//PCIE_RX_EXPECTED_SEQNUM
#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM__SHIFT                                                    0x0
#define PCIE_RX_EXPECTED_SEQNUM__RX_EXPECTED_SEQNUM_MASK                                                      0x00000FFFL
//PCIE_RX_VENDOR_SPECIFIC
#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA__SHIFT                                                        0x0
#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS__SHIFT                                                      0x18
#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_DATA_MASK                                                          0x00FFFFFFL
#define PCIE_RX_VENDOR_SPECIFIC__RX_VENDOR_STATUS_MASK                                                        0x01000000L
//PCIE_RX_CNTL3
#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR__SHIFT                                                   0x0
#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR__SHIFT                                                   0x1
#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR__SHIFT                                                      0x2
#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR__SHIFT                                                          0x3
#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR__SHIFT                                                     0x4
#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMRDPASID_UR_MASK                                                     0x00000001L
#define PCIE_RX_CNTL3__RX_IGNORE_RC_TRANSMWRPASID_UR_MASK                                                     0x00000002L
#define PCIE_RX_CNTL3__RX_IGNORE_RC_PRGRESPMSG_UR_MASK                                                        0x00000004L
#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVREQ_UR_MASK                                                            0x00000008L
#define PCIE_RX_CNTL3__RX_IGNORE_RC_INVCPLPASID_UR_MASK                                                       0x00000010L
//PCIE_RX_CREDITS_ALLOCATED_P
#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD__SHIFT                                           0x0
#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH__SHIFT                                           0x10
#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PD_MASK                                             0x00000FFFL
#define PCIE_RX_CREDITS_ALLOCATED_P__RX_CREDITS_ALLOCATED_PH_MASK                                             0x00FF0000L
//PCIE_RX_CREDITS_ALLOCATED_NP
#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD__SHIFT                                         0x0
#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH__SHIFT                                         0x10
#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPD_MASK                                           0x00000FFFL
#define PCIE_RX_CREDITS_ALLOCATED_NP__RX_CREDITS_ALLOCATED_NPH_MASK                                           0x00FF0000L
//PCIE_RX_CREDITS_ALLOCATED_CPL
#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD__SHIFT                                       0x0
#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH__SHIFT                                       0x10
#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLD_MASK                                         0x00000FFFL
#define PCIE_RX_CREDITS_ALLOCATED_CPL__RX_CREDITS_ALLOCATED_CPLH_MASK                                         0x00FF0000L
//PCIEP_ERROR_INJECT_PHYSICAL
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR__SHIFT                                          0x0
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR__SHIFT                                       0x2
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP__SHIFT                                 0x4
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP__SHIFT                                   0x6
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW__SHIFT                                    0x8
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW__SHIFT                                    0xa
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR__SHIFT                                        0xc
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR__SHIFT                               0xe
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR__SHIFT                                  0x10
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR__SHIFT                                      0x12
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER__SHIFT                                 0x14
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER__SHIFT                                   0x16
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LANE_ERR_MASK                                            0x00000003L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_FRAMING_ERR_MASK                                         0x0000000CL
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_PARITY_IN_SKP_MASK                                   0x00000030L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_LFSR_IN_SKP_MASK                                     0x000000C0L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_UFLOW_MASK                                      0x00000300L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_LOOPBACK_OFLOW_MASK                                      0x00000C00L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_DESKEW_ERR_MASK                                          0x00003000L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DISPARITY_ERR_MASK                                 0x0000C000L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_8B10B_DECODE_ERR_MASK                                    0x00030000L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_SKP_OS_ERROR_MASK                                        0x000C0000L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_INV_OS_IDENTIFIER_MASK                                   0x00300000L
#define PCIEP_ERROR_INJECT_PHYSICAL__ERROR_INJECT_PL_BAD_SYNC_HEADER_MASK                                     0x00C00000L
//PCIEP_ERROR_INJECT_TRANSACTION
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR__SHIFT                                   0x0
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER__SHIFT                            0x2
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP__SHIFT                                       0x4
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP__SHIFT                                        0x6
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ__SHIFT                                0x8
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR__SHIFT                                     0xa
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP__SHIFT                                  0xc
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT__SHIFT                               0xe
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT__SHIFT                                0x10
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT__SHIFT                             0x12
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_FLOW_CTL_ERR_MASK                                     0x00000003L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER_MASK                              0x0000000CL
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_DLLP_MASK                                         0x00000030L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_BAD_TLP_MASK                                          0x000000C0L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNSUPPORTED_REQ_MASK                                  0x00000300L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_ECRC_ERROR_MASK                                       0x00000C00L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_MALFORMED_TLP_MASK                                    0x00003000L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_UNEXPECTED_CMPLT_MASK                                 0x0000C000L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETER_ABORT_MASK                                  0x00030000L
#define PCIEP_ERROR_INJECT_TRANSACTION__ERROR_INJECT_TL_COMPLETION_TIMEOUT_MASK                               0x000C0000L
//PCIEP_SRIOV_PRIV_CTRL
#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE__SHIFT                                                0x0
#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT                                          0x2
#define PCIEP_SRIOV_PRIV_CTRL__RX_SRIOV_VF_MAPPING_MODE_MASK                                                  0x00000003L
#define PCIEP_SRIOV_PRIV_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK                                            0x0000000CL
//PCIEP_NAK_COUNTER
#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT__SHIFT                                                    0x0
#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT__SHIFT                                                   0x10
#define PCIEP_NAK_COUNTER__RX_NUM_NAK_RECEIVED_PORT_MASK                                                      0x0000FFFFL
#define PCIEP_NAK_COUNTER__RX_NUM_NAK_GENERATED_PORT_MASK                                                     0xFFFF0000L
//PCIE_LC_CNTL
#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0__SHIFT                                                          0x1
#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN__SHIFT                                                         0x2
#define PCIE_LC_CNTL__LC_RESET_LINK__SHIFT                                                                    0x3
#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE__SHIFT                                                             0x4
#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT                                                                0x8
#define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT                                                                 0xc
#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT                                                                 0x10
#define PCIE_LC_CNTL__LC_INC_N_FTS_EN__SHIFT                                                                  0x11
#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23__SHIFT                                                        0x12
#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC__SHIFT                                                            0x14
#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS__SHIFT                                                           0x15
#define PCIE_LC_CNTL__LC_WAKE_FROM_L23__SHIFT                                                                 0x16
#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK__SHIFT                                                              0x17
#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS__SHIFT                                                                0x18
#define PCIE_LC_CNTL__LC_DELAY_COUNT__SHIFT                                                                   0x19
#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT__SHIFT                                                                0x1b
#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT__SHIFT                                                                 0x1c
#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE__SHIFT                                                       0x1d
#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN__SHIFT                                                               0x1e
#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE__SHIFT                                                                0x1f
#define PCIE_LC_CNTL__LC_DONT_ENTER_L23_IN_D0_MASK                                                            0x00000002L
#define PCIE_LC_CNTL__LC_RESET_L_IDLE_COUNT_EN_MASK                                                           0x00000004L
#define PCIE_LC_CNTL__LC_RESET_LINK_MASK                                                                      0x00000008L
#define PCIE_LC_CNTL__LC_16X_CLEAR_TX_PIPE_MASK                                                               0x000000F0L
#define PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK                                                                  0x00000F00L
#define PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK                                                                   0x0000F000L
#define PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK                                                                   0x00010000L
#define PCIE_LC_CNTL__LC_INC_N_FTS_EN_MASK                                                                    0x00020000L
#define PCIE_LC_CNTL__LC_LOOK_FOR_IDLE_IN_L1L23_MASK                                                          0x000C0000L
#define PCIE_LC_CNTL__LC_FACTOR_IN_EXT_SYNC_MASK                                                              0x00100000L
#define PCIE_LC_CNTL__LC_WAIT_FOR_PM_ACK_DIS_MASK                                                             0x00200000L
#define PCIE_LC_CNTL__LC_WAKE_FROM_L23_MASK                                                                   0x00400000L
#define PCIE_LC_CNTL__LC_L1_IMMEDIATE_ACK_MASK                                                                0x00800000L
#define PCIE_LC_CNTL__LC_ASPM_TO_L1_DIS_MASK                                                                  0x01000000L
#define PCIE_LC_CNTL__LC_DELAY_COUNT_MASK                                                                     0x06000000L
#define PCIE_LC_CNTL__LC_DELAY_L0S_EXIT_MASK                                                                  0x08000000L
#define PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK                                                                   0x10000000L
#define PCIE_LC_CNTL__LC_EXTEND_WAIT_FOR_EL_IDLE_MASK                                                         0x20000000L
#define PCIE_LC_CNTL__LC_ESCAPE_L1L23_EN_MASK                                                                 0x40000000L
#define PCIE_LC_CNTL__LC_GATE_RCVR_IDLE_MASK                                                                  0x80000000L
//PCIE_LC_TRAINING_CNTL
#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL__SHIFT                                                        0x0
#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE__SHIFT                                                   0x4
#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1__SHIFT                                       0x5
#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN__SHIFT                                              0x6
#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN__SHIFT                                                  0x7
#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE__SHIFT                                                          0x8
#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED__SHIFT                                           0xb
#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN__SHIFT                                             0xc
#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH__SHIFT                                            0xd
#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG__SHIFT                                                0xe
#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN__SHIFT                                              0xf
#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP__SHIFT                                                  0x10
#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF__SHIFT                                                0x11
#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF__SHIFT                                                  0x12
#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN__SHIFT                                                       0x13
#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW__SHIFT                                                       0x14
#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN__SHIFT                                              0x15
#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL__SHIFT                                                0x16
#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED__SHIFT                                       0x18
#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST__SHIFT                                          0x19
#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER__SHIFT                                              0x1a
#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT__SHIFT                                                   0x1b
#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL__SHIFT                                                  0x1c
#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK__SHIFT                                       0x1d
#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME__SHIFT                                                   0x1e
#define PCIE_LC_TRAINING_CNTL__LC_TRAINING_CNTL_MASK                                                          0x0000000FL
#define PCIE_LC_TRAINING_CNTL__LC_COMPLIANCE_RECEIVE_MASK                                                     0x00000010L
#define PCIE_LC_TRAINING_CNTL__LC_LOOK_FOR_MORE_NON_MATCHING_TS1_MASK                                         0x00000020L
#define PCIE_LC_TRAINING_CNTL__LC_L0S_L1_TRAINING_CNTL_EN_MASK                                                0x00000040L
#define PCIE_LC_TRAINING_CNTL__LC_L1_LONG_WAKE_FIX_EN_MASK                                                    0x00000080L
#define PCIE_LC_TRAINING_CNTL__LC_POWER_STATE_MASK                                                            0x00000700L
#define PCIE_LC_TRAINING_CNTL__LC_DONT_GO_TO_L0S_IF_L1_ARMED_MASK                                             0x00000800L
#define PCIE_LC_TRAINING_CNTL__LC_INIT_SPD_CHG_WITH_CSR_EN_MASK                                               0x00001000L
#define PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK                                              0x00002000L
#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_SETS_IN_RCFG_MASK                                                  0x00004000L
#define PCIE_LC_TRAINING_CNTL__LC_HOT_RESET_QUICK_EXIT_EN_MASK                                                0x00008000L
#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_WAIT_FOR_SKP_MASK                                                    0x00010000L
#define PCIE_LC_TRAINING_CNTL__LC_AUTONOMOUS_CHANGE_OFF_MASK                                                  0x00020000L
#define PCIE_LC_TRAINING_CNTL__LC_UPCONFIGURE_CAP_OFF_MASK                                                    0x00040000L
#define PCIE_LC_TRAINING_CNTL__LC_HW_LINK_DIS_EN_MASK                                                         0x00080000L
#define PCIE_LC_TRAINING_CNTL__LC_LINK_DIS_BY_HW_MASK                                                         0x00100000L
#define PCIE_LC_TRAINING_CNTL__LC_STATIC_TX_PIPE_COUNT_EN_MASK                                                0x00200000L
#define PCIE_LC_TRAINING_CNTL__LC_ASPM_L1_NAK_TIMER_SEL_MASK                                                  0x00C00000L
#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_R_SPEED_MASK                                         0x01000000L
#define PCIE_LC_TRAINING_CNTL__LC_DONT_DEASSERT_RX_EN_IN_TEST_MASK                                            0x02000000L
#define PCIE_LC_TRAINING_CNTL__LC_RESET_ASPM_L1_NAK_TIMER_MASK                                                0x04000000L
#define PCIE_LC_TRAINING_CNTL__LC_SHORT_RCFG_TIMEOUT_MASK                                                     0x08000000L
#define PCIE_LC_TRAINING_CNTL__LC_ALLOW_TX_L1_CONTROL_MASK                                                    0x10000000L
#define PCIE_LC_TRAINING_CNTL__LC_WAIT_FOR_FOM_VALID_AFTER_TRACK_MASK                                         0x20000000L
#define PCIE_LC_TRAINING_CNTL__LC_EXTEND_EQ_REQ_TIME_MASK                                                     0xC0000000L
//PCIE_LC_LINK_WIDTH_CNTL
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT                                                         0x0
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT                                                      0x4
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE__SHIFT                                        0x7
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW__SHIFT                                                       0x8
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT__SHIFT                                              0x9
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN__SHIFT                                                     0xa
#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN__SHIFT                                                  0xb
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT__SHIFT                                                0xc
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS__SHIFT                                                    0xd
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS__SHIFT                                            0xe
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL__SHIFT                                                    0xf
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB__SHIFT                                                   0x10
#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT                                                     0x11
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN__SHIFT                                                     0x12
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN__SHIFT                                               0x13
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE__SHIFT                                                0x14
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT                                                0x15
#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN__SHIFT                                               0x17
#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN__SHIFT                                             0x18
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN__SHIFT                                        0x19
#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE__SHIFT                                          0x1a
#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT__SHIFT                                      0x1b
#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE__SHIFT                                      0x1c
#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI__SHIFT                                           0x1d
#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES__SHIFT                                              0x1e
#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS__SHIFT                                            0x1f
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK                                                           0x00000007L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK                                                        0x00000070L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_ARC_MISSING_ESCAPE_MASK                                          0x00000080L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK                                                         0x00000100L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK                                                0x00000200L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK                                                       0x00000400L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_SHORT_RECONFIG_EN_MASK                                                    0x00000800L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK                                                  0x00001000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK                                                      0x00002000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_WAIT_FOR_RCVR_DIS_MASK                                              0x00004000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCFG_TIMER_SEL_MASK                                                      0x00008000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DEASSERT_TX_PDNB_MASK                                                     0x00010000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK                                                       0x00020000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYNLINK_MST_EN_MASK                                                       0x00040000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DUAL_END_RECONFIG_EN_MASK                                                 0x00080000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_CAPABLE_MASK                                                  0x00100000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK                                                  0x00600000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_EQ_REVERSAL_LOGIC_EN_MASK                                                 0x00800000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_MULT_REVERSE_ATTEMP_EN_MASK                                               0x01000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_RESET_TSX_CNT_IN_RCONFIG_EN_MASK                                          0x02000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_L_IDLE_IN_R_IDLE_MASK                                            0x04000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT_MASK                                        0x08000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE_MASK                                        0x10000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXL0S_ON_SHORT_EI_MASK                                             0x20000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_TURN_OFF_UNUSED_LANES_MASK                                                0x40000000L
#define PCIE_LC_LINK_WIDTH_CNTL__LC_BYPASS_RXSTANDBY_STATUS_MASK                                              0x80000000L
//PCIE_LC_N_FTS_CNTL
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT                                                              0x0
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN__SHIFT                                                  0x8
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY__SHIFT                                                0x9
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL__SHIFT                                                     0xf
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT__SHIFT                                                        0x10
#define PCIE_LC_N_FTS_CNTL__LC_N_FTS__SHIFT                                                                   0x18
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK                                                                0x000000FFL
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK                                                    0x00000100L
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_FTS_BEFORE_RECOVERY_MASK                                                  0x00000200L
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_8GT_CNTL_MASK                                                       0x00008000L
#define PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_LIMIT_MASK                                                          0x00FF0000L
#define PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK                                                                     0xFF000000L
//PSWUSP0_PCIE_LC_SPEED_CNTL
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                                   0x0
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                                   0x1
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN__SHIFT                                   0x2
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE__SHIFT                                      0x3
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE__SHIFT                                        0x5
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE__SHIFT                                       0x6
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE__SHIFT                                        0x7
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE__SHIFT                                       0x8
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE__SHIFT                                      0x9
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                   0xa
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                     0xc
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT                                               0xd
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS__SHIFT                               0xf
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT__SHIFT                                       0x10
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN__SHIFT                                      0x11
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2__SHIFT                                       0x12
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2__SHIFT                                        0x13
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3__SHIFT                                       0x14
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3__SHIFT                                        0x15
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS__SHIFT                                               0x16
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS__SHIFT                                             0x17
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED__SHIFT                                            0x18
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE__SHIFT                                                 0x1a
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN__SHIFT                                  0x1b
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN__SHIFT                                        0x1c
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN__SHIFT                                         0x1d
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG__SHIFT                                         0x1e
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS__SHIFT                                          0x1f
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                                     0x00000001L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                                     0x00000002L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_EN_MASK                                     0x00000004L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_TARGET_LINK_SPEED_OVERRIDE_MASK                                        0x00000018L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK                                          0x00000020L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK                                         0x00000040L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_EN_HW_SPEED_CHANGE_MASK                                          0x00000080L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK                                         0x00000100L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK                                        0x00000200L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                     0x00000C00L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                       0x00001000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK                                                 0x00006000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS_MASK                                 0x00008000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CLR_FAILED_SPD_CHANGE_CNT_MASK                                         0x00010000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_1_OR_MORE_TS2_SPEED_ARC_EN_MASK                                        0x00020000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN2_MASK                                         0x00040000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN2_MASK                                          0x00080000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_EVER_SENT_GEN3_MASK                                         0x00100000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_OTHER_SIDE_SUPPORTS_GEN3_MASK                                          0x00200000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_AUTO_RECOVERY_DIS_MASK                                                 0x00400000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_SPEED_CHANGE_STATUS_MASK                                               0x00800000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DATA_RATE_ADVERTISED_MASK                                              0x03000000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CHECK_DATA_RATE_MASK                                                   0x04000000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN_MASK                                    0x08000000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L0s_EN_MASK                                          0x10000000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_INIT_SPEED_NEG_IN_L1_EN_MASK                                           0x20000000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DONT_CHECK_EQTS_IN_RCFG_MASK                                           0x40000000L
#define PSWUSP0_PCIE_LC_SPEED_CNTL__LC_DELAY_COEFF_UPDATE_DIS_MASK                                            0x80000000L
//PCIE_LC_STATE0
#define PCIE_LC_STATE0__LC_CURRENT_STATE__SHIFT                                                               0x0
#define PCIE_LC_STATE0__LC_PREV_STATE1__SHIFT                                                                 0x8
#define PCIE_LC_STATE0__LC_PREV_STATE2__SHIFT                                                                 0x10
#define PCIE_LC_STATE0__LC_PREV_STATE3__SHIFT                                                                 0x18
#define PCIE_LC_STATE0__LC_CURRENT_STATE_MASK                                                                 0x0000003FL
#define PCIE_LC_STATE0__LC_PREV_STATE1_MASK                                                                   0x00003F00L
#define PCIE_LC_STATE0__LC_PREV_STATE2_MASK                                                                   0x003F0000L
#define PCIE_LC_STATE0__LC_PREV_STATE3_MASK                                                                   0x3F000000L
//PCIE_LC_STATE1
#define PCIE_LC_STATE1__LC_PREV_STATE4__SHIFT                                                                 0x0
#define PCIE_LC_STATE1__LC_PREV_STATE5__SHIFT                                                                 0x8
#define PCIE_LC_STATE1__LC_PREV_STATE6__SHIFT                                                                 0x10
#define PCIE_LC_STATE1__LC_PREV_STATE7__SHIFT                                                                 0x18
#define PCIE_LC_STATE1__LC_PREV_STATE4_MASK                                                                   0x0000003FL
#define PCIE_LC_STATE1__LC_PREV_STATE5_MASK                                                                   0x00003F00L
#define PCIE_LC_STATE1__LC_PREV_STATE6_MASK                                                                   0x003F0000L
#define PCIE_LC_STATE1__LC_PREV_STATE7_MASK                                                                   0x3F000000L
//PCIE_LC_STATE2
#define PCIE_LC_STATE2__LC_PREV_STATE8__SHIFT                                                                 0x0
#define PCIE_LC_STATE2__LC_PREV_STATE9__SHIFT                                                                 0x8
#define PCIE_LC_STATE2__LC_PREV_STATE10__SHIFT                                                                0x10
#define PCIE_LC_STATE2__LC_PREV_STATE11__SHIFT                                                                0x18
#define PCIE_LC_STATE2__LC_PREV_STATE8_MASK                                                                   0x0000003FL
#define PCIE_LC_STATE2__LC_PREV_STATE9_MASK                                                                   0x00003F00L
#define PCIE_LC_STATE2__LC_PREV_STATE10_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE2__LC_PREV_STATE11_MASK                                                                  0x3F000000L
//PCIE_LC_STATE3
#define PCIE_LC_STATE3__LC_PREV_STATE12__SHIFT                                                                0x0
#define PCIE_LC_STATE3__LC_PREV_STATE13__SHIFT                                                                0x8
#define PCIE_LC_STATE3__LC_PREV_STATE14__SHIFT                                                                0x10
#define PCIE_LC_STATE3__LC_PREV_STATE15__SHIFT                                                                0x18
#define PCIE_LC_STATE3__LC_PREV_STATE12_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE3__LC_PREV_STATE13_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE3__LC_PREV_STATE14_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE3__LC_PREV_STATE15_MASK                                                                  0x3F000000L
//PCIE_LC_STATE4
#define PCIE_LC_STATE4__LC_PREV_STATE16__SHIFT                                                                0x0
#define PCIE_LC_STATE4__LC_PREV_STATE17__SHIFT                                                                0x8
#define PCIE_LC_STATE4__LC_PREV_STATE18__SHIFT                                                                0x10
#define PCIE_LC_STATE4__LC_PREV_STATE19__SHIFT                                                                0x18
#define PCIE_LC_STATE4__LC_PREV_STATE16_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE4__LC_PREV_STATE17_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE4__LC_PREV_STATE18_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE4__LC_PREV_STATE19_MASK                                                                  0x3F000000L
//PCIE_LC_STATE5
#define PCIE_LC_STATE5__LC_PREV_STATE20__SHIFT                                                                0x0
#define PCIE_LC_STATE5__LC_PREV_STATE21__SHIFT                                                                0x8
#define PCIE_LC_STATE5__LC_PREV_STATE22__SHIFT                                                                0x10
#define PCIE_LC_STATE5__LC_PREV_STATE23__SHIFT                                                                0x18
#define PCIE_LC_STATE5__LC_PREV_STATE20_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE5__LC_PREV_STATE21_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE5__LC_PREV_STATE22_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE5__LC_PREV_STATE23_MASK                                                                  0x3F000000L
//PCIE_LINK_MANAGEMENT_CNTL2
#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD__SHIFT                                                       0x0
#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT__SHIFT                                                       0x1
#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD__SHIFT                                                        0x2
#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT__SHIFT                                                        0x3
#define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE__SHIFT                                                       0x4
#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2__SHIFT                                                0x7
#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2__SHIFT                                               0xb
#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3__SHIFT                                                0xf
#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3__SHIFT                                               0x13
#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_RCVD_MASK                                                         0x00000001L
#define PCIE_LINK_MANAGEMENT_CNTL2__QUIESCE_SENT_MASK                                                         0x00000002L
#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_RCVD_MASK                                                          0x00000004L
#define PCIE_LINK_MANAGEMENT_CNTL2__REQ_EQ_SENT_MASK                                                          0x00000008L
#define PCIE_LINK_MANAGEMENT_CNTL2__BW_HINT_MODE_MASK                                                         0x00000070L
#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G2_MASK                                                  0x00000780L
#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G2_MASK                                                 0x00007800L
#define PCIE_LINK_MANAGEMENT_CNTL2__LOW_BW_THRESHOLD_G3_MASK                                                  0x00078000L
#define PCIE_LINK_MANAGEMENT_CNTL2__HIGH_BW_THRESHOLD_G3_MASK                                                 0x00780000L
//PSWUSP0_PCIE_LC_CNTL2
#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE__SHIFT                                                      0x0
#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT__SHIFT                                                      0x6
#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION__SHIFT                                                0x7
#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN__SHIFT                                                          0x8
#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS__SHIFT                                                  0x9
#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN__SHIFT                                                  0xa
#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE__SHIFT                                                        0xb
#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN__SHIFT                                             0xc
#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE__SHIFT                                            0xd
#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE__SHIFT                                                       0xe
#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET__SHIFT                                       0x10
#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1__SHIFT                                                     0x11
#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23__SHIFT                                                    0x12
#define PSWUSP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S__SHIFT                                                0x13
#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0__SHIFT                                                  0x14
#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS__SHIFT                                                0x15
#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD__SHIFT                                          0x16
#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG__SHIFT                                             0x17
#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES__SHIFT                                               0x19
#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS__SHIFT                                           0x1a
#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                             0x1b
#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE__SHIFT                                             0x1c
#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL__SHIFT                                                       0x1d
#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI__SHIFT                                     0x1f
#define PSWUSP0_PCIE_LC_CNTL2__LC_TIMED_OUT_STATE_MASK                                                        0x0000003FL
#define PSWUSP0_PCIE_LC_CNTL2__LC_STATE_TIMED_OUT_MASK                                                        0x00000040L
#define PSWUSP0_PCIE_LC_CNTL2__LC_LOOK_FOR_BW_REDUCTION_MASK                                                  0x00000080L
#define PSWUSP0_PCIE_LC_CNTL2__LC_MORE_TS2_EN_MASK                                                            0x00000100L
#define PSWUSP0_PCIE_LC_CNTL2__LC_X12_NEGOTIATION_DIS_MASK                                                    0x00000200L
#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_UP_REVERSAL_EN_MASK                                                    0x00000400L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_MASK                                                          0x00000800L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ILLEGAL_STATE_RESTART_EN_MASK                                               0x00001000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_OTHER_LANES_MODE_MASK                                              0x00002000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ELEC_IDLE_MODE_MASK                                                         0x0000C000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_INFERRED_ELEC_IDLE_DET_MASK                                         0x00010000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK                                                       0x00020000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK                                                      0x00040000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_DEASSERT_RX_EN_IN_L0S_MASK                                                  0x00080000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_BLOCK_EL_IDLE_IN_L0_MASK                                                    0x00100000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK                                                  0x00200000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ASSERT_INACTIVE_DURING_HOLD_MASK                                            0x00400000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_WAIT_FOR_LANES_IN_LW_NEG_MASK                                               0x01800000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_PWR_DOWN_NEG_OFF_LANES_MASK                                                 0x02000000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_DISABLE_LOST_SYM_LOCK_ARCS_MASK                                             0x04000000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                               0x08000000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_PMI_L1_WAIT_FOR_SLV_IDLE_MASK                                               0x10000000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_TEST_TIMER_SEL_MASK                                                         0x60000000L
#define PSWUSP0_PCIE_LC_CNTL2__LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI_MASK                                       0x80000000L
//PCIE_LC_BW_CHANGE_CNTL
#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN__SHIFT                                                    0x0
#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE__SHIFT                                                0x1
#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE__SHIFT                                                0x2
#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE__SHIFT                                             0x3
#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE__SHIFT                                            0x4
#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG__SHIFT                                                    0x5
#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE__SHIFT                                                      0x6
#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE__SHIFT                                                     0x7
#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER__SHIFT                                                     0x8
#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED__SHIFT                                                    0x9
#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE__SHIFT                                    0xa
#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL__SHIFT                                              0xb
#define PCIE_LC_BW_CHANGE_CNTL__LC_BW_CHANGE_INT_EN_MASK                                                      0x00000001L
#define PCIE_LC_BW_CHANGE_CNTL__LC_HW_INIT_SPEED_CHANGE_MASK                                                  0x00000002L
#define PCIE_LC_BW_CHANGE_CNTL__LC_SW_INIT_SPEED_CHANGE_MASK                                                  0x00000004L
#define PCIE_LC_BW_CHANGE_CNTL__LC_OTHER_INIT_SPEED_CHANGE_MASK                                               0x00000008L
#define PCIE_LC_BW_CHANGE_CNTL__LC_RELIABILITY_SPEED_CHANGE_MASK                                              0x00000010L
#define PCIE_LC_BW_CHANGE_CNTL__LC_FAILED_SPEED_NEG_MASK                                                      0x00000020L
#define PCIE_LC_BW_CHANGE_CNTL__LC_LONG_LW_CHANGE_MASK                                                        0x00000040L
#define PCIE_LC_BW_CHANGE_CNTL__LC_SHORT_LW_CHANGE_MASK                                                       0x00000080L
#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_OTHER_MASK                                                       0x00000100L
#define PCIE_LC_BW_CHANGE_CNTL__LC_LW_CHANGE_FAILED_MASK                                                      0x00000200L
#define PCIE_LC_BW_CHANGE_CNTL__LC_LINK_BW_NOTIFICATION_DETECT_MODE_MASK                                      0x00000400L
#define PCIE_LC_BW_CHANGE_CNTL__LC_SPEED_NEG_UNSUCCESSFUL_MASK                                                0x00000800L
//PCIE_LC_CDR_CNTL
#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF__SHIFT                                                              0x0
#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS__SHIFT                                                             0xc
#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE__SHIFT                                                              0x18
#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_OFF_MASK                                                                0x00000FFFL
#define PCIE_LC_CDR_CNTL__LC_CDR_TEST_SETS_MASK                                                               0x00FFF000L
#define PCIE_LC_CDR_CNTL__LC_CDR_SET_TYPE_MASK                                                                0x03000000L
//PCIE_LC_LANE_CNTL
#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES__SHIFT                                                          0x0
#define PCIE_LC_LANE_CNTL__LC_LANE_DIS__SHIFT                                                                 0x10
#define PCIE_LC_LANE_CNTL__LC_CORRUPTED_LANES_MASK                                                            0x0000FFFFL
#define PCIE_LC_LANE_CNTL__LC_LANE_DIS_MASK                                                                   0xFFFF0000L
//PCIE_LC_CNTL3
#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS__SHIFT                                                            0x0
#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL__SHIFT                                                       0x1
#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS__SHIFT                                                              0x3
#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT__SHIFT                                                               0x4
#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN__SHIFT                                                    0x5
#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED__SHIFT                                           0x6
#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                             0x8
#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT__SHIFT                                               0x9
#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN__SHIFT                                                         0xa
#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE__SHIFT                                                         0xb
#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD__SHIFT                                                               0xc
#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD__SHIFT                                                               0xe
#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN__SHIFT                                                         0x10
#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN__SHIFT                                                         0x11
#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN__SHIFT                                                0x12
#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL__SHIFT                                      0x13
#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN__SHIFT                                                        0x15
#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE__SHIFT                                                    0x16
#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK__SHIFT                                             0x17
#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL__SHIFT                                                        0x18
#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL__SHIFT                                                            0x1a
#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY__SHIFT                                                               0x1e
#define PCIE_LC_CNTL3__LC_N_EIE_SEL__SHIFT                                                                    0x1f
#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_MASK                                                              0x00000001L
#define PCIE_LC_CNTL3__LC_SELECT_DEEMPHASIS_CNTL_MASK                                                         0x00000006L
#define PCIE_LC_CNTL3__LC_RCVD_DEEMPHASIS_MASK                                                                0x00000008L
#define PCIE_LC_CNTL3__LC_COMP_TO_DETECT_MASK                                                                 0x00000010L
#define PCIE_LC_CNTL3__LC_RESET_TSX_CNT_IN_RLOCK_EN_MASK                                                      0x00000020L
#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK                                             0x000000C0L
#define PCIE_LC_CNTL3__LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                               0x00000100L
#define PCIE_LC_CNTL3__LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT_MASK                                                 0x00000200L
#define PCIE_LC_CNTL3__LC_ENHANCED_HOT_PLUG_EN_MASK                                                           0x00000400L
#define PCIE_LC_CNTL3__LC_RCVR_DET_EN_OVERRIDE_MASK                                                           0x00000800L
#define PCIE_LC_CNTL3__LC_EHP_RX_PHY_CMD_MASK                                                                 0x00003000L
#define PCIE_LC_CNTL3__LC_EHP_TX_PHY_CMD_MASK                                                                 0x0000C000L
#define PCIE_LC_CNTL3__LC_CHIP_BIF_USB_IDLE_EN_MASK                                                           0x00010000L
#define PCIE_LC_CNTL3__LC_L1_BLOCK_RECONFIG_EN_MASK                                                           0x00020000L
#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_EN_MASK                                                  0x00040000L
#define PCIE_LC_CNTL3__LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL_MASK                                        0x00180000L
#define PCIE_LC_CNTL3__LC_FAST_L1_ENTRY_EXIT_EN_MASK                                                          0x00200000L
#define PCIE_LC_CNTL3__LC_RXPHYCMD_INACTIVE_EN_MODE_MASK                                                      0x00400000L
#define PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK                                               0x00800000L
#define PCIE_LC_CNTL3__LC_HW_VOLTAGE_IF_CONTROL_MASK                                                          0x03000000L
#define PCIE_LC_CNTL3__LC_VOLTAGE_TIMER_SEL_MASK                                                              0x3C000000L
#define PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK                                                                 0x40000000L
#define PCIE_LC_CNTL3__LC_N_EIE_SEL_MASK                                                                      0x80000000L
//PCIE_LC_CNTL4
#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR__SHIFT                                                          0x0
#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK__SHIFT                                                     0x2
#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE__SHIFT                                                  0x3
#define PCIE_LC_CNTL4__LC_BYPASS_EQ__SHIFT                                                                    0x4
#define PCIE_LC_CNTL4__LC_REDO_EQ__SHIFT                                                                      0x5
#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS__SHIFT                                                                 0x6
#define PCIE_LC_CNTL4__LC_IGNORE_PARITY__SHIFT                                                                0x7
#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE__SHIFT                                                               0x8
#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK__SHIFT                                                    0xa
#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD__SHIFT                                                              0xb
#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ__SHIFT                                                                 0xc
#define PCIE_LC_CNTL4__LC_SET_QUIESCE__SHIFT                                                                  0xd
#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD__SHIFT                                                                 0xe
#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD__SHIFT                                                       0xf
#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE__SHIFT                                                          0x10
#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE__SHIFT                                                 0x11
#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE__SHIFT                                                           0x12
#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS__SHIFT                                                              0x16
#define PCIE_LC_CNTL4__LC_TX_SWING__SHIFT                                                                     0x17
#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE__SHIFT                                                        0x18
#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN__SHIFT                                                            0x19
#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK__SHIFT                                                    0x1a
#define PCIE_LC_CNTL4__LC_TX_ENABLE_BEHAVIOUR_MASK                                                            0x00000003L
#define PCIE_LC_CNTL4__LC_DIS_CONTIG_END_SET_CHECK_MASK                                                       0x00000004L
#define PCIE_LC_CNTL4__LC_DIS_ASPM_L1_IN_SPEED_CHANGE_MASK                                                    0x00000008L
#define PCIE_LC_CNTL4__LC_BYPASS_EQ_MASK                                                                      0x00000010L
#define PCIE_LC_CNTL4__LC_REDO_EQ_MASK                                                                        0x00000020L
#define PCIE_LC_CNTL4__LC_EXTEND_EIEOS_MASK                                                                   0x00000040L
#define PCIE_LC_CNTL4__LC_IGNORE_PARITY_MASK                                                                  0x00000080L
#define PCIE_LC_CNTL4__LC_EQ_SEARCH_MODE_MASK                                                                 0x00000300L
#define PCIE_LC_CNTL4__LC_DSC_CHECK_COEFFS_IN_RLOCK_MASK                                                      0x00000400L
#define PCIE_LC_CNTL4__LC_USC_EQ_NOT_REQD_MASK                                                                0x00000800L
#define PCIE_LC_CNTL4__LC_USC_GO_TO_EQ_MASK                                                                   0x00001000L
#define PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK                                                                    0x00002000L
#define PCIE_LC_CNTL4__LC_QUIESCE_RCVD_MASK                                                                   0x00004000L
#define PCIE_LC_CNTL4__LC_UNEXPECTED_COEFFS_RCVD_MASK                                                         0x00008000L
#define PCIE_LC_CNTL4__LC_BYPASS_EQ_REQ_PHASE_MASK                                                            0x00010000L
#define PCIE_LC_CNTL4__LC_FORCE_PRESET_IN_EQ_REQ_PHASE_MASK                                                   0x00020000L
#define PCIE_LC_CNTL4__LC_FORCE_PRESET_VALUE_MASK                                                             0x003C0000L
#define PCIE_LC_CNTL4__LC_USC_DELAY_DLLPS_MASK                                                                0x00400000L
#define PCIE_LC_CNTL4__LC_TX_SWING_MASK                                                                       0x00800000L
#define PCIE_LC_CNTL4__LC_EQ_WAIT_FOR_EVAL_DONE_MASK                                                          0x01000000L
#define PCIE_LC_CNTL4__LC_8GT_SKIP_ORDER_EN_MASK                                                              0x02000000L
#define PCIE_LC_CNTL4__LC_WAIT_FOR_MORE_TS_IN_RLOCK_MASK                                                      0xFC000000L
//PCIE_LC_CNTL5
#define PCIE_LC_CNTL5__LC_EQ_FS_0__SHIFT                                                                      0x0
#define PCIE_LC_CNTL5__LC_EQ_FS_8__SHIFT                                                                      0x6
#define PCIE_LC_CNTL5__LC_EQ_LF_0__SHIFT                                                                      0xc
#define PCIE_LC_CNTL5__LC_EQ_LF_8__SHIFT                                                                      0x12
#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS__SHIFT                                              0x18
#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE__SHIFT                                                            0x19
#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS__SHIFT                                                           0x1a
#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST__SHIFT                                                      0x1b
#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT__SHIFT                                                               0x1c
#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE__SHIFT                                                           0x1d
#define PCIE_LC_CNTL5__LC_EQ_FS_0_MASK                                                                        0x0000003FL
#define PCIE_LC_CNTL5__LC_EQ_FS_8_MASK                                                                        0x00000FC0L
#define PCIE_LC_CNTL5__LC_EQ_LF_0_MASK                                                                        0x0003F000L
#define PCIE_LC_CNTL5__LC_EQ_LF_8_MASK                                                                        0x00FC0000L
#define PCIE_LC_CNTL5__LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS_MASK                                                0x01000000L
#define PCIE_LC_CNTL5__LC_TX_SWING_OVERRIDE_MASK                                                              0x02000000L
#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_MASK                                                             0x04000000L
#define PCIE_LC_CNTL5__LC_ACCEPT_ALL_PRESETS_TEST_MASK                                                        0x08000000L
#define PCIE_LC_CNTL5__LC_WAIT_IN_DETECT_MASK                                                                 0x10000000L
#define PCIE_LC_CNTL5__LC_HOLD_TRAINING_MODE_MASK                                                             0xE0000000L
//PCIE_LC_FORCE_COEFF
#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF__SHIFT                                                            0x0
#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR__SHIFT                                                       0x1
#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR__SHIFT                                                           0x7
#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR__SHIFT                                                      0xd
#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN__SHIFT                                                    0x13
#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN__SHIFT                                                           0x14
#define PCIE_LC_FORCE_COEFF__LC_FORCE_COEFF_MASK                                                              0x00000001L
#define PCIE_LC_FORCE_COEFF__LC_FORCE_PRE_CURSOR_MASK                                                         0x0000007EL
#define PCIE_LC_FORCE_COEFF__LC_FORCE_CURSOR_MASK                                                             0x00001F80L
#define PCIE_LC_FORCE_COEFF__LC_FORCE_POST_CURSOR_MASK                                                        0x0007E000L
#define PCIE_LC_FORCE_COEFF__LC_3X3_COEFF_SEARCH_EN_MASK                                                      0x00080000L
#define PCIE_LC_FORCE_COEFF__LC_PRESET_10_EN_MASK                                                             0x00100000L
//PCIE_LC_BEST_EQ_SETTINGS
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET__SHIFT                                                       0x0
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR__SHIFT                                                    0x4
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR__SHIFT                                                       0xa
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR__SHIFT                                                   0x10
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM__SHIFT                                                          0x16
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRESET_MASK                                                         0x0000000FL
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_PRECURSOR_MASK                                                      0x000003F0L
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_CURSOR_MASK                                                         0x0000FC00L
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_POSTCURSOR_MASK                                                     0x003F0000L
#define PCIE_LC_BEST_EQ_SETTINGS__LC_BEST_FOM_MASK                                                            0x3FC00000L
//PCIE_LC_FORCE_EQ_REQ_COEFF
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE__SHIFT                                     0x0
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ__SHIFT                                            0x1
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ__SHIFT                                                0x7
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ__SHIFT                                           0xd
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END__SHIFT                                                    0x13
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END__SHIFT                                                    0x19
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_COEFF_IN_EQ_REQ_PHASE_MASK                                       0x00000001L
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_PRE_CURSOR_REQ_MASK                                              0x0000007EL
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_CURSOR_REQ_MASK                                                  0x00001F80L
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FORCE_POST_CURSOR_REQ_MASK                                             0x0007E000L
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_FS_OTHER_END_MASK                                                      0x01F80000L
#define PCIE_LC_FORCE_EQ_REQ_COEFF__LC_LF_OTHER_END_MASK                                                      0x7E000000L
//PCIE_LC_CNTL6
#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT__SHIFT                                                               0x0
#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT__SHIFT                                                                 0x2
#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT                                                                 0x4
#define PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK__SHIFT                                                      0x5
#define PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT__SHIFT                                                   0x6
#define PCIE_LC_CNTL6__LC_SRIS_EN__SHIFT                                                                      0x8
#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS__SHIFT                                                            0x9
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN__SHIFT                                                           0xd
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR__SHIFT                                                       0xe
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE__SHIFT                                                         0x10
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE__SHIFT                                                 0x12
#define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN__SHIFT                                                      0x13
#define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG__SHIFT                                                           0x14
#define PCIE_LC_CNTL6__LC_L1_POWERDOWN__SHIFT                                                                 0x15
#define PCIE_LC_CNTL6__LC_P2_ENTRY__SHIFT                                                                     0x16
#define PCIE_LC_CNTL6__LC_RXRECOVER_EN__SHIFT                                                                 0x17
#define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT__SHIFT                                                            0x18
#define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN__SHIFT                                                            0x1f
#define PCIE_LC_CNTL6__LC_SPC_MODE_2P5GT_MASK                                                                 0x00000001L
#define PCIE_LC_CNTL6__LC_SPC_MODE_5GT_MASK                                                                   0x00000004L
#define PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK                                                                   0x00000010L
#define PCIE_LC_CNTL6__LC_WAIT_FOR_EIEOS_IN_RLOCK_MASK                                                        0x00000020L
#define PCIE_LC_CNTL6__LC_DYNAMIC_INACTIVE_TS_SELECT_MASK                                                     0x000000C0L
#define PCIE_LC_CNTL6__LC_SRIS_EN_MASK                                                                        0x00000100L
#define PCIE_LC_CNTL6__LC_SRNS_SKIP_IN_SRIS_MASK                                                              0x00001E00L
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_EN_MASK                                                             0x00002000L
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_FACTOR_MASK                                                         0x0000C000L
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_MODE_MASK                                                           0x00030000L
#define PCIE_LC_CNTL6__LC_SRIS_AUTODETECT_OUT_OF_RANGE_MASK                                                   0x00040000L
#define PCIE_LC_CNTL6__LC_DEFER_SKIP_FOR_EIEOS_EN_MASK                                                        0x00080000L
#define PCIE_LC_CNTL6__LC_SEND_EIEOS_IN_RCFG_MASK                                                             0x00100000L
#define PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK                                                                   0x00200000L
#define PCIE_LC_CNTL6__LC_P2_ENTRY_MASK                                                                       0x00400000L
#define PCIE_LC_CNTL6__LC_RXRECOVER_EN_MASK                                                                   0x00800000L
#define PCIE_LC_CNTL6__LC_RXRECOVER_TIMEOUT_MASK                                                              0x7F000000L
#define PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK                                                              0x80000000L
//PCIE_LC_CNTL7
#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE__SHIFT                                                    0x0
#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG__SHIFT                                               0x1
#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN__SHIFT                                                   0x2
#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI__SHIFT                                                         0x3
#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN__SHIFT                                                           0x4
#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK__SHIFT                                                           0x8
#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN__SHIFT                                                    0x9
#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1__SHIFT                                                0xc
#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL__SHIFT                                                  0xd
#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE__SHIFT                                                      0x15
#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN__SHIFT                                               0x16
#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN__SHIFT                                                           0x17
#define PCIE_LC_CNTL7__LC_FOM_TIME__SHIFT                                                                     0x18
#define PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH__SHIFT                                                               0x1a
#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE__SHIFT                                                           0x1b
#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE__SHIFT                                                            0x1c
#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT__SHIFT                                                                0x1d
#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM__SHIFT                                                                0x1e
#define PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN__SHIFT                                                    0x1f
#define PCIE_LC_CNTL7__LC_EXPECTED_TS2_CFG_COMPLETE_MASK                                                      0x00000001L
#define PCIE_LC_CNTL7__LC_IGNORE_NON_CONTIG_SETS_IN_RCFG_MASK                                                 0x00000002L
#define PCIE_LC_CNTL7__LC_ROBUST_TRAINING_BIT_CHK_EN_MASK                                                     0x00000004L
#define PCIE_LC_CNTL7__LC_RESET_TS_COUNT_ON_EI_MASK                                                           0x00000008L
#define PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK                                                             0x00000010L
#define PCIE_LC_CNTL7__LC_EVER_IDLE_TO_RLOCK_MASK                                                             0x00000100L
#define PCIE_LC_CNTL7__LC_RXEQEVAL_AFTER_TIMEOUT_EN_MASK                                                      0x00000200L
#define PCIE_LC_CNTL7__LC_ESM_WAIT_FOR_PLL_INIT_DONE_L1_MASK                                                  0x00001000L
#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_INTERVAL_MASK                                                    0x001FE000L
#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_MODE_MASK                                                        0x00200000L
#define PCIE_LC_CNTL7__LC_SCHEDULED_RXEQEVAL_UPCONFIG_EN_MASK                                                 0x00400000L
#define PCIE_LC_CNTL7__LC_LINK_MANAGEMENT_EN_MASK                                                             0x00800000L
#define PCIE_LC_CNTL7__LC_FOM_TIME_MASK                                                                       0x03000000L
#define PCIE_LC_CNTL7__LC_SAFE_EQ_SEARCH_MASK                                                                 0x04000000L
#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_STATE_MASK                                                             0x08000000L
#define PCIE_LC_CNTL7__LC_ESM_PLL_INIT_DONE_MASK                                                              0x10000000L
#define PCIE_LC_CNTL7__LC_ESM_REDO_INIT_MASK                                                                  0x20000000L
#define PCIE_LC_CNTL7__LC_MULTIPORT_ESM_MASK                                                                  0x40000000L
#define PCIE_LC_CNTL7__LC_CONSECUTIVE_EIOS_RESET_EN_MASK                                                      0x80000000L
//PCIE_LINK_MANAGEMENT_STATUS
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE__SHIFT                                                 0x0
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED__SHIFT                                  0x1
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE__SHIFT                                 0x2
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE__SHIFT                                                 0x3
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED__SHIFT                                  0x4
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE__SHIFT                                 0x5
#define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE__SHIFT                                       0x6
#define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE__SHIFT                                                  0x7
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE__SHIFT                                           0x8
#define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT__SHIFT                                               0x9
#define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST__SHIFT                                              0xa
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST__SHIFT                                          0xb
#define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE__SHIFT                                          0xc
#define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS__SHIFT                                        0xd
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_UPDATE_MASK                                                   0x00000001L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK                                    0x00000002L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK                                   0x00000004L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_UPDATE_MASK                                                   0x00000008L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK                                    0x00000010L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK                                   0x00000020L
#define PCIE_LINK_MANAGEMENT_STATUS__POWER_DOWN_COMMAND_COMPLETE_MASK                                         0x00000040L
#define PCIE_LINK_MANAGEMENT_STATUS__BANDWIDTH_UPDATE_MASK                                                    0x00000080L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_POWER_STATE_CHANGE_MASK                                             0x00000100L
#define PCIE_LINK_MANAGEMENT_STATUS__BW_REQUIREMENT_HINT_MASK                                                 0x00000200L
#define PCIE_LINK_MANAGEMENT_STATUS__EQUALIZATION_REQUEST_MASK                                                0x00000400L
#define PCIE_LINK_MANAGEMENT_STATUS__LINK_PARTNER_ESM_REQUEST_MASK                                            0x00000800L
#define PCIE_LINK_MANAGEMENT_STATUS__LOW_SPEED_REQD_IMMEDIATE_MASK                                            0x00001000L
#define PCIE_LINK_MANAGEMENT_STATUS__ESTABLISH_ESM_PLL_SETTINGS_MASK                                          0x00002000L
//PCIE_LINK_MANAGEMENT_MASK
#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK__SHIFT                                              0x0
#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                               0x1
#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK__SHIFT                              0x2
#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK__SHIFT                                              0x3
#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK__SHIFT                               0x4
#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK__SHIFT                              0x5
#define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK__SHIFT                                    0x6
#define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK__SHIFT                                               0x7
#define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK__SHIFT                                        0x8
#define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK__SHIFT                                            0x9
#define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK__SHIFT                                           0xa
#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK__SHIFT                                       0xb
#define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK__SHIFT                                       0xc
#define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK__SHIFT                                     0xd
#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_UPDATE_MASK_MASK                                                0x00000001L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_SPEED_CHANGE_ATTEMPT_FAILED_MASK_MASK                                 0x00000002L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_SPEED_SUPPORT_UPDATE_MASK_MASK                                0x00000004L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_UPDATE_MASK_MASK                                                0x00000008L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_WIDTH_CHANGE_ATTEMPT_FAILED_MASK_MASK                                 0x00000010L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_WIDTH_SUPPORT_UPDATE_MASK_MASK                                0x00000020L
#define PCIE_LINK_MANAGEMENT_MASK__POWER_DOWN_COMMAND_COMPLETE_MASK_MASK                                      0x00000040L
#define PCIE_LINK_MANAGEMENT_MASK__BANDWIDTH_UPDATE_MASK_MASK                                                 0x00000080L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_POWER_STATE_CHANGE_MASK_MASK                                          0x00000100L
#define PCIE_LINK_MANAGEMENT_MASK__BW_REQUIREMENT_HINT_MASK_MASK                                              0x00000200L
#define PCIE_LINK_MANAGEMENT_MASK__EQUALIZATION_REQUEST_MASK_MASK                                             0x00000400L
#define PCIE_LINK_MANAGEMENT_MASK__LINK_PARTNER_ESM_REQUEST_MASK_MASK                                         0x00000800L
#define PCIE_LINK_MANAGEMENT_MASK__LOW_SPEED_REQD_IMMEDIATE_MASK_MASK                                         0x00001000L
#define PCIE_LINK_MANAGEMENT_MASK__ESTABLISH_ESM_PLL_SETTINGS_MASK_MASK                                       0x00002000L
//PCIE_LINK_MANAGEMENT_CNTL
#define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT__SHIFT                                               0x0
#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE__SHIFT                                                    0x3
#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK__SHIFT                                               0x7
#define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP__SHIFT                                                             0xb
#define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN__SHIFT                                                   0xc
#define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE__SHIFT                                                            0xd
#define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE__SHIFT                                                          0xf
#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT__SHIFT                                                         0x11
#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT__SHIFT                                                        0x12
#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD__SHIFT                                                    0x13
#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD__SHIFT                                                   0x17
#define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT__SHIFT                                                       0x1b
#define PCIE_LINK_MANAGEMENT_CNTL__FAR_END_WIDTH_SUPPORT_MASK                                                 0x00000007L
#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK                                                      0x00000078L
#define PCIE_LINK_MANAGEMENT_CNTL__LINK_POWER_STATE_MASK_MASK                                                 0x00000780L
#define PCIE_LINK_MANAGEMENT_CNTL__LINK_UP_MASK                                                               0x00000800L
#define PCIE_LINK_MANAGEMENT_CNTL__PORT_POWERED_DOWN_MASK                                                     0x00001000L
#define PCIE_LINK_MANAGEMENT_CNTL__SPC_MODE_MASK                                                              0x00006000L
#define PCIE_LINK_MANAGEMENT_CNTL__CLOCK_RATE_MASK                                                            0x00018000L
#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_HINT_MASK                                                           0x00020000L
#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_HINT_MASK                                                          0x00040000L
#define PCIE_LINK_MANAGEMENT_CNTL__LOW_BW_THRESHOLD_MASK                                                      0x00780000L
#define PCIE_LINK_MANAGEMENT_CNTL__HIGH_BW_THRESHOLD_MASK                                                     0x07800000L
#define PCIE_LINK_MANAGEMENT_CNTL__BW_HINT_COUNT_MASK                                                         0x38000000L
//PCIEP_STRAP_LC
#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT__SHIFT                                                           0x0
#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT__SHIFT                                                          0x2
#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT__SHIFT                                                           0x4
#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT__SHIFT                                                         0x6
#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL__SHIFT                                                            0x8
#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET__SHIFT                                                          0xb
#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS__SHIFT                                                           0xc
#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE__SHIFT                                                         0xd
#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES__SHIFT                                                         0xe
#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS__SHIFT                                            0xf
#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION__SHIFT                                                         0x10
#define PCIEP_STRAP_LC__STRAP_FTS_yTSx_COUNT_MASK                                                             0x00000003L
#define PCIEP_STRAP_LC__STRAP_LONG_yTSx_COUNT_MASK                                                            0x0000000CL
#define PCIEP_STRAP_LC__STRAP_MED_yTSx_COUNT_MASK                                                             0x00000030L
#define PCIEP_STRAP_LC__STRAP_SHORT_yTSx_COUNT_MASK                                                           0x000000C0L
#define PCIEP_STRAP_LC__STRAP_SKIP_INTERVAL_MASK                                                              0x00000700L
#define PCIEP_STRAP_LC__STRAP_BYPASS_RCVR_DET_MASK                                                            0x00000800L
#define PCIEP_STRAP_LC__STRAP_COMPLIANCE_DIS_MASK                                                             0x00001000L
#define PCIEP_STRAP_LC__STRAP_FORCE_COMPLIANCE_MASK                                                           0x00002000L
#define PCIEP_STRAP_LC__STRAP_REVERSE_LC_LANES_MASK                                                           0x00004000L
#define PCIEP_STRAP_LC__STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS_MASK                                              0x00008000L
#define PCIEP_STRAP_LC__STRAP_LANE_NEGOTIATION_MASK                                                           0x00070000L
//PSWUSP0_PCIEP_STRAP_MISC
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES__SHIFT                                                  0x0
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN__SHIFT                                                  0x1
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED__SHIFT                                         0x2
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED__SHIFT                                                 0x3
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED__SHIFT                                                  0x5
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_REVERSE_LANES_MASK                                                    0x00000001L
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_E2E_PREFIX_EN_MASK                                                    0x00000002L
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_EXTENDED_FMT_SUPPORTED_MASK                                           0x00000004L
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_OBFF_SUPPORTED_MASK                                                   0x00000018L
#define PSWUSP0_PCIEP_STRAP_MISC__STRAP_LTR_SUPPORTED_MASK                                                    0x00000020L
//PCIE_LC_L1_PM_SUBSTATE
#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN__SHIFT                                            0x0
#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE__SHIFT                                                0x1
#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE__SHIFT                                                0x2
#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE__SHIFT                                                  0x3
#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE__SHIFT                                                  0x4
#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE__SHIFT                                                    0x6
#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE__SHIFT                                                    0x8
#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN__SHIFT                                                      0x10
#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN__SHIFT                                                      0x14
#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK                                              0x00000001L
#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK                                                  0x00000002L
#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_1_OVERRIDE_MASK                                                  0x00000004L
#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_2_OVERRIDE_MASK                                                    0x00000008L
#define PCIE_LC_L1_PM_SUBSTATE__LC_ASPM_L1_1_OVERRIDE_MASK                                                    0x00000010L
#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_SCALE_MASK                                                      0x000000C0L
#define PCIE_LC_L1_PM_SUBSTATE__LC_T_POWER_ON_VALUE_MASK                                                      0x00001F00L
#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_1_POWERDOWN_MASK                                                        0x00070000L
#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_2_POWERDOWN_MASK                                                        0x00700000L
//PCIE_LC_L1_PM_SUBSTATE2
#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME__SHIFT                                                    0x0
#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE__SHIFT                                                0x8
#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE__SHIFT                                                0x10
#define PCIE_LC_L1_PM_SUBSTATE2__LC_CM_RESTORE_TIME_MASK                                                      0x000000FFL
#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_SCALE_MASK                                                  0x00000700L
#define PCIE_LC_L1_PM_SUBSTATE2__LC_LTR_THRESHOLD_VALUE_MASK                                                  0x03FF0000L
//PCIE_LC_PORT_ORDER
#define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET__SHIFT                                                             0x0
#define PCIE_LC_PORT_ORDER__LC_PORT_OFFSET_MASK                                                               0x0000000FL
//PCIEP_BCH_ECC_CNTL
#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN__SHIFT                                                           0x0
#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD__SHIFT                                                    0x8
#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS__SHIFT                                                       0x10
#define PCIEP_BCH_ECC_CNTL__STRAP_BCH_ECC_EN_MASK                                                             0x00000001L
#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_THRESHOLD_MASK                                                      0x0000FF00L
#define PCIEP_BCH_ECC_CNTL__BCH_ECC_ERROR_STATUS_MASK                                                         0xFFFF0000L


// addressBlock: nbio_pcie_pciedir
//PCIE_RESERVED
#define PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                                   0x0
#define PCIE_RESERVED__PCIE_RESERVED_MASK                                                                     0xFFFFFFFFL
//PCIE_SCRATCH
#define PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                                     0x0
#define PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                                       0xFFFFFFFFL
//PCIE_RX_NUM_NAK
#define PCIE_RX_NUM_NAK__RX_NUM_NAK__SHIFT                                                                    0x0
#define PCIE_RX_NUM_NAK__RX_NUM_NAK_MASK                                                                      0xFFFFFFFFL
//PCIE_RX_NUM_NAK_GENERATED
#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED__SHIFT                                                0x0
#define PCIE_RX_NUM_NAK_GENERATED__RX_NUM_NAK_GENERATED_MASK                                                  0xFFFFFFFFL
//PCIE_CNTL
#define PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                                      0x0
#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL__SHIFT                                                               0x1
#define PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                                   0x7
#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                                             0x8
#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE__SHIFT                                                                0x9
#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE__SHIFT                                                              0xa
#define PCIE_CNTL__RX_RCB_ATS_UC_DIS__SHIFT                                                                   0xf
#define PCIE_CNTL__RX_RCB_REORDER_EN__SHIFT                                                                   0x10
#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS__SHIFT                                                             0x11
#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS__SHIFT                                                                0x12
#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE__SHIFT                                                        0x13
#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS__SHIFT                                                             0x14
#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS__SHIFT                                                               0x15
#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS__SHIFT                                                            0x16
#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS__SHIFT                                                           0x17
#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                                                0x1e
#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN__SHIFT                                                            0x1f
#define PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                                        0x00000001L
#define PCIE_CNTL__LC_HOT_PLUG_DELAY_SEL_MASK                                                                 0x0000000EL
#define PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                                     0x00000080L
#define PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                                               0x00000100L
#define PCIE_CNTL__PCIE_HT_NP_MEM_WRITE_MASK                                                                  0x00000200L
#define PCIE_CNTL__RX_SB_ADJ_PAYLOAD_SIZE_MASK                                                                0x00001C00L
#define PCIE_CNTL__RX_RCB_ATS_UC_DIS_MASK                                                                     0x00008000L
#define PCIE_CNTL__RX_RCB_REORDER_EN_MASK                                                                     0x00010000L
#define PCIE_CNTL__RX_RCB_INVALID_SIZE_DIS_MASK                                                               0x00020000L
#define PCIE_CNTL__RX_RCB_UNEXP_CPL_DIS_MASK                                                                  0x00040000L
#define PCIE_CNTL__RX_RCB_CPL_TIMEOUT_TEST_MODE_MASK                                                          0x00080000L
#define PCIE_CNTL__RX_RCB_WRONG_PREFIX_DIS_MASK                                                               0x00100000L
#define PCIE_CNTL__RX_RCB_WRONG_ATTR_DIS_MASK                                                                 0x00200000L
#define PCIE_CNTL__RX_RCB_WRONG_FUNCNUM_DIS_MASK                                                              0x00400000L
#define PCIE_CNTL__RX_ATS_TRAN_CPL_SPLIT_DIS_MASK                                                             0x00800000L
#define PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                                  0x40000000L
#define PCIE_CNTL__RX_CPL_POSTED_REQ_ORD_EN_MASK                                                              0x80000000L
//PCIE_CONFIG_CNTL
#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT                                                              0x0
#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE__SHIFT                                                0x8
#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                0x9
#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE__SHIFT                                                     0x10
#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                     0x11
#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE__SHIFT                                                0x14
#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                                0x15
#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE__SHIFT                                                        0x18
#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                                  0x19
#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT                                           0x1b
#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT                                           0x1c
#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                             0x1e
#define PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK                                                                0x0000000FL
#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_PAYLOAD_SIZE_MODE_MASK                                                  0x00000100L
#define PCIE_CONFIG_CNTL__CI_SWUS_PRIV_MAX_PAYLOAD_SIZE_MASK                                                  0x00000600L
#define PCIE_CONFIG_CNTL__CI_MAX_PAYLOAD_SIZE_MODE_MASK                                                       0x00010000L
#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_PAYLOAD_SIZE_MASK                                                       0x000E0000L
#define PCIE_CONFIG_CNTL__CI_MAX_READ_REQUEST_SIZE_MODE_MASK                                                  0x00100000L
#define PCIE_CONFIG_CNTL__CI_PRIV_MAX_READ_REQUEST_SIZE_MASK                                                  0x00E00000L
#define PCIE_CONFIG_CNTL__CI_MAX_READ_SAFE_MODE_MASK                                                          0x01000000L
#define PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                                    0x06000000L
#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK                                             0x08000000L
#define PCIE_CONFIG_CNTL__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK                                             0x30000000L
#define PCIE_CONFIG_CNTL__CI_SWUS_EXTENDED_TAG_EN_OVERRIDE_MASK                                               0xC0000000L
//PCIE_TX_TRACKING_ADDR_LO
#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO__SHIFT                                                  0x2
#define PCIE_TX_TRACKING_ADDR_LO__TX_TRACKING_ADDR_LO_MASK                                                    0xFFFFFFFCL
//PCIE_TX_TRACKING_ADDR_HI
#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI__SHIFT                                                  0x0
#define PCIE_TX_TRACKING_ADDR_HI__TX_TRACKING_ADDR_HI_MASK                                                    0xFFFFFFFFL
//PCIE_TX_TRACKING_CTRL_STATUS
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE__SHIFT                                               0x0
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT__SHIFT                                                 0x1
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID__SHIFT                                              0x8
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID__SHIFT                                         0xf
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_ENABLE_MASK                                                 0x00000001L
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_PORT_MASK                                                   0x0000000EL
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_UNIT_ID_MASK                                                0x00007F00L
#define PCIE_TX_TRACKING_CTRL_STATUS__TX_TRACKING_STATUS_VALID_MASK                                           0x00008000L
//PCIE_BW_BY_UNITID
#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN__SHIFT                                                       0x0
#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID__SHIFT                                                          0x8
#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_EN_MASK                                                         0x00000001L
#define PCIE_BW_BY_UNITID__CI_MST_PERF_UNITID_MASK                                                            0x00007F00L
//PCIE_CNTL2
#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN__SHIFT                                                              0x0
#define PCIE_CNTL2__TX_ARB_SLV_LIMIT__SHIFT                                                                   0x1
#define PCIE_CNTL2__TX_ARB_MST_LIMIT__SHIFT                                                                   0x6
#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS__SHIFT                                                             0xb
#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING__SHIFT                                                       0xc
#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE__SHIFT                                                              0xd
#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS__SHIFT                                                             0xe
#define PCIE_CNTL2__SLV_MEM_LS_EN__SHIFT                                                                      0x10
#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN__SHIFT                                                           0x11
#define PCIE_CNTL2__MST_MEM_LS_EN__SHIFT                                                                      0x12
#define PCIE_CNTL2__REPLAY_MEM_LS_EN__SHIFT                                                                   0x13
#define PCIE_CNTL2__SLV_MEM_SD_EN__SHIFT                                                                      0x14
#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN__SHIFT                                                           0x15
#define PCIE_CNTL2__MST_MEM_SD_EN__SHIFT                                                                      0x16
#define PCIE_CNTL2__REPLAY_MEM_SD_EN__SHIFT                                                                   0x17
#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING__SHIFT                                                           0x18
#define PCIE_CNTL2__SLV_MEM_DS_EN__SHIFT                                                                      0x1d
#define PCIE_CNTL2__MST_MEM_DS_EN__SHIFT                                                                      0x1e
#define PCIE_CNTL2__REPLAY_MEM_DS_EN__SHIFT                                                                   0x1f
#define PCIE_CNTL2__TX_ARB_ROUND_ROBIN_EN_MASK                                                                0x00000001L
#define PCIE_CNTL2__TX_ARB_SLV_LIMIT_MASK                                                                     0x0000003EL
#define PCIE_CNTL2__TX_ARB_MST_LIMIT_MASK                                                                     0x000007C0L
#define PCIE_CNTL2__TX_BLOCK_TLP_ON_PM_DIS_MASK                                                               0x00000800L
#define PCIE_CNTL2__TX_NP_MEM_WRITE_SWP_ENCODING_MASK                                                         0x00001000L
#define PCIE_CNTL2__TX_ATOMIC_OPS_DISABLE_MASK                                                                0x00002000L
#define PCIE_CNTL2__TX_ATOMIC_ORDERING_DIS_MASK                                                               0x00004000L
#define PCIE_CNTL2__SLV_MEM_LS_EN_MASK                                                                        0x00010000L
#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_LS_EN_MASK                                                             0x00020000L
#define PCIE_CNTL2__MST_MEM_LS_EN_MASK                                                                        0x00040000L
#define PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK                                                                     0x00080000L
#define PCIE_CNTL2__SLV_MEM_SD_EN_MASK                                                                        0x00100000L
#define PCIE_CNTL2__SLV_MEM_AGGRESSIVE_SD_EN_MASK                                                             0x00200000L
#define PCIE_CNTL2__MST_MEM_SD_EN_MASK                                                                        0x00400000L
#define PCIE_CNTL2__REPLAY_MEM_SD_EN_MASK                                                                     0x00800000L
#define PCIE_CNTL2__RX_NP_MEM_WRITE_ENCODING_MASK                                                             0x1F000000L
#define PCIE_CNTL2__SLV_MEM_DS_EN_MASK                                                                        0x20000000L
#define PCIE_CNTL2__MST_MEM_DS_EN_MASK                                                                        0x40000000L
#define PCIE_CNTL2__REPLAY_MEM_DS_EN_MASK                                                                     0x80000000L
//PCIE_RX_CNTL2
#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                                    0x0
#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR__SHIFT                                                        0x1
#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR__SHIFT                                                        0x2
#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR__SHIFT                                                     0x3
#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR__SHIFT                                                      0x4
#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR__SHIFT                                                          0x5
#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN__SHIFT                                                               0x8
#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE__SHIFT                                                            0x9
#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN__SHIFT                                                                0xc
#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN__SHIFT                                                                0xd
#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN__SHIFT                                                                0xe
#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT__SHIFT                                                        0x10
#define PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                                                 0x1c
#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                                      0x00000001L
#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMRD_UR_MASK                                                          0x00000002L
#define PCIE_RX_CNTL2__RX_IGNORE_EP_TRANSMWR_UR_MASK                                                          0x00000004L
#define PCIE_RX_CNTL2__RX_IGNORE_EP_ATSTRANSREQ_UR_MASK                                                       0x00000008L
#define PCIE_RX_CNTL2__RX_IGNORE_EP_PAGEREQMSG_UR_MASK                                                        0x00000010L
#define PCIE_RX_CNTL2__RX_IGNORE_EP_INVCPL_UR_MASK                                                            0x00000020L
#define PCIE_RX_CNTL2__RX_RCB_LATENCY_EN_MASK                                                                 0x00000100L
#define PCIE_RX_CNTL2__RX_RCB_LATENCY_SCALE_MASK                                                              0x00000E00L
#define PCIE_RX_CNTL2__SLVCPL_MEM_LS_EN_MASK                                                                  0x00001000L
#define PCIE_RX_CNTL2__SLVCPL_MEM_SD_EN_MASK                                                                  0x00002000L
#define PCIE_RX_CNTL2__SLVCPL_MEM_DS_EN_MASK                                                                  0x00004000L
#define PCIE_RX_CNTL2__RX_RCB_LATENCY_MAX_COUNT_MASK                                                          0x03FF0000L
#define PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                                   0x70000000L
//PCIE_TX_F0_ATTR_CNTL
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P__SHIFT                                                     0x0
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP__SHIFT                                                    0x2
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL__SHIFT                                                   0x4
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P__SHIFT                                                      0x6
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP__SHIFT                                                     0x8
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P__SHIFT                                                     0xa
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP__SHIFT                                                    0xc
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_P_MASK                                                       0x00000003L
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_NP_MASK                                                      0x0000000CL
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_IDO_OVERRIDE_CPL_MASK                                                     0x00000030L
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_P_MASK                                                        0x000000C0L
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_RO_OVERRIDE_NP_MASK                                                       0x00000300L
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_P_MASK                                                       0x00000C00L
#define PCIE_TX_F0_ATTR_CNTL__TX_F0_SNR_OVERRIDE_NP_MASK                                                      0x00003000L
//PCIE_TX_SWUS_ATTR_CNTL
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P__SHIFT                                                 0x0
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP__SHIFT                                                0x2
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL__SHIFT                                               0x4
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P__SHIFT                                                  0x6
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP__SHIFT                                                 0x8
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P__SHIFT                                                 0xa
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP__SHIFT                                                0xc
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_P_MASK                                                   0x00000003L
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_NP_MASK                                                  0x0000000CL
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_IDO_OVERRIDE_CPL_MASK                                                 0x00000030L
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_P_MASK                                                    0x000000C0L
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_RO_OVERRIDE_NP_MASK                                                   0x00000300L
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_P_MASK                                                   0x00000C00L
#define PCIE_TX_SWUS_ATTR_CNTL__TX_SWUS_SNR_OVERRIDE_NP_MASK                                                  0x00003000L
//PCIE_CI_CNTL
#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE__SHIFT                                                              0x2
#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS__SHIFT                                                             0x3
#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA__SHIFT                                                           0x4
#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE__SHIFT                                                            0x6
#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS__SHIFT                                                              0x8
#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS__SHIFT                                                               0x9
#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS__SHIFT                                                             0xa
#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE__SHIFT                                                            0xb
#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR__SHIFT                                                             0xc
#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS__SHIFT                                              0x10
#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS__SHIFT                                                  0x11
#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS__SHIFT                                         0x12
#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS__SHIFT                                             0x13
#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS__SHIFT                                                     0x14
#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG__SHIFT                                                    0x15
#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN__SHIFT                                                           0x16
#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN__SHIFT                                                       0x17
#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN__SHIFT                                                         0x18
#define PCIE_CI_CNTL__CI_SLAVE_SPLIT_MODE_MASK                                                                0x00000004L
#define PCIE_CI_CNTL__CI_SLAVE_GEN_USR_DIS_MASK                                                               0x00000008L
#define PCIE_CI_CNTL__CI_MST_CMPL_DUMMY_DATA_MASK                                                             0x00000010L
#define PCIE_CI_CNTL__CI_SLV_RC_RD_REQ_SIZE_MASK                                                              0x000000C0L
#define PCIE_CI_CNTL__CI_SLV_ORDERING_DIS_MASK                                                                0x00000100L
#define PCIE_CI_CNTL__CI_RC_ORDERING_DIS_MASK                                                                 0x00000200L
#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_DIS_MASK                                                               0x00000400L
#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_MODE_MASK                                                              0x00000800L
#define PCIE_CI_CNTL__CI_SLV_CPL_ALLOC_SOR_MASK                                                               0x00001000L
#define PCIE_CI_CNTL__CI_SLV_SDP_ERR_DATA_ON_POISONED_DIS_MASK                                                0x00010000L
#define PCIE_CI_CNTL__TX_PRIV_TLP_PREFIX_BLOCKING_DIS_MASK                                                    0x00020000L
#define PCIE_CI_CNTL__TX_PRIV_POISONED_TLP_EGRESS_BLOCKING_DIS_MASK                                           0x00040000L
#define PCIE_CI_CNTL__TX_PRIV_ATOMICOP_EGRESS_BLOCKING_DIS_MASK                                               0x00080000L
#define PCIE_CI_CNTL__PRIV_AUTO_SLOT_PWR_LIMIT_DIS_MASK                                                       0x00100000L
#define PCIE_CI_CNTL__TX_DISABLE_SLOT_PWR_LIMIT_MSG_MASK                                                      0x00200000L
#define PCIE_CI_CNTL__RX_RCB_RC_CTO_TO_UR_EN_MASK                                                             0x00400000L
#define PCIE_CI_CNTL__RX_RCB_RC_DPC_EXCEPTION_EN_MASK                                                         0x00800000L
#define PCIE_CI_CNTL__RX_RCB_RC_DPC_CPL_CTL_EN_MASK                                                           0x01000000L
//PCIE_BUS_CNTL
#define PCIE_BUS_CNTL__PMI_INT_DIS__SHIFT                                                                     0x6
#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                                               0x7
#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN__SHIFT                                                               0xc
#define PCIE_BUS_CNTL__PMI_INT_DIS_MASK                                                                       0x00000040L
#define PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                                 0x00000080L
#define PCIE_BUS_CNTL__TRUE_PM_STATUS_EN_MASK                                                                 0x00001000L
//PCIE_LC_STATE6
#define PCIE_LC_STATE6__LC_PREV_STATE24__SHIFT                                                                0x0
#define PCIE_LC_STATE6__LC_PREV_STATE25__SHIFT                                                                0x8
#define PCIE_LC_STATE6__LC_PREV_STATE26__SHIFT                                                                0x10
#define PCIE_LC_STATE6__LC_PREV_STATE27__SHIFT                                                                0x18
#define PCIE_LC_STATE6__LC_PREV_STATE24_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE6__LC_PREV_STATE25_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE6__LC_PREV_STATE26_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE6__LC_PREV_STATE27_MASK                                                                  0x3F000000L
//PCIE_LC_STATE7
#define PCIE_LC_STATE7__LC_PREV_STATE28__SHIFT                                                                0x0
#define PCIE_LC_STATE7__LC_PREV_STATE29__SHIFT                                                                0x8
#define PCIE_LC_STATE7__LC_PREV_STATE30__SHIFT                                                                0x10
#define PCIE_LC_STATE7__LC_PREV_STATE31__SHIFT                                                                0x18
#define PCIE_LC_STATE7__LC_PREV_STATE28_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE7__LC_PREV_STATE29_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE7__LC_PREV_STATE30_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE7__LC_PREV_STATE31_MASK                                                                  0x3F000000L
//PCIE_LC_STATE8
#define PCIE_LC_STATE8__LC_PREV_STATE32__SHIFT                                                                0x0
#define PCIE_LC_STATE8__LC_PREV_STATE33__SHIFT                                                                0x8
#define PCIE_LC_STATE8__LC_PREV_STATE34__SHIFT                                                                0x10
#define PCIE_LC_STATE8__LC_PREV_STATE35__SHIFT                                                                0x18
#define PCIE_LC_STATE8__LC_PREV_STATE32_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE8__LC_PREV_STATE33_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE8__LC_PREV_STATE34_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE8__LC_PREV_STATE35_MASK                                                                  0x3F000000L
//PCIE_LC_STATE9
#define PCIE_LC_STATE9__LC_PREV_STATE36__SHIFT                                                                0x0
#define PCIE_LC_STATE9__LC_PREV_STATE37__SHIFT                                                                0x8
#define PCIE_LC_STATE9__LC_PREV_STATE38__SHIFT                                                                0x10
#define PCIE_LC_STATE9__LC_PREV_STATE39__SHIFT                                                                0x18
#define PCIE_LC_STATE9__LC_PREV_STATE36_MASK                                                                  0x0000003FL
#define PCIE_LC_STATE9__LC_PREV_STATE37_MASK                                                                  0x00003F00L
#define PCIE_LC_STATE9__LC_PREV_STATE38_MASK                                                                  0x003F0000L
#define PCIE_LC_STATE9__LC_PREV_STATE39_MASK                                                                  0x3F000000L
//PCIE_LC_STATE10
#define PCIE_LC_STATE10__LC_PREV_STATE40__SHIFT                                                               0x0
#define PCIE_LC_STATE10__LC_PREV_STATE41__SHIFT                                                               0x8
#define PCIE_LC_STATE10__LC_PREV_STATE42__SHIFT                                                               0x10
#define PCIE_LC_STATE10__LC_PREV_STATE43__SHIFT                                                               0x18
#define PCIE_LC_STATE10__LC_PREV_STATE40_MASK                                                                 0x0000003FL
#define PCIE_LC_STATE10__LC_PREV_STATE41_MASK                                                                 0x00003F00L
#define PCIE_LC_STATE10__LC_PREV_STATE42_MASK                                                                 0x003F0000L
#define PCIE_LC_STATE10__LC_PREV_STATE43_MASK                                                                 0x3F000000L
//PCIE_LC_STATE11
#define PCIE_LC_STATE11__LC_PREV_STATE44__SHIFT                                                               0x0
#define PCIE_LC_STATE11__LC_PREV_STATE45__SHIFT                                                               0x8
#define PCIE_LC_STATE11__LC_PREV_STATE46__SHIFT                                                               0x10
#define PCIE_LC_STATE11__LC_PREV_STATE47__SHIFT                                                               0x18
#define PCIE_LC_STATE11__LC_PREV_STATE44_MASK                                                                 0x0000003FL
#define PCIE_LC_STATE11__LC_PREV_STATE45_MASK                                                                 0x00003F00L
#define PCIE_LC_STATE11__LC_PREV_STATE46_MASK                                                                 0x003F0000L
#define PCIE_LC_STATE11__LC_PREV_STATE47_MASK                                                                 0x3F000000L
//PCIE_LC_STATUS1
#define PCIE_LC_STATUS1__LC_REVERSE_RCVR__SHIFT                                                               0x0
#define PCIE_LC_STATUS1__LC_REVERSE_XMIT__SHIFT                                                               0x1
#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT                                                       0x2
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT                                                        0x5
#define PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK                                                                 0x00000001L
#define PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK                                                                 0x00000002L
#define PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK                                                         0x0000001CL
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK                                                          0x000000E0L
//PCIE_LC_STATUS2
#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES__SHIFT                                                       0x0
#define PCIE_LC_STATUS2__LC_TURN_ON_LANE__SHIFT                                                               0x10
#define PCIE_LC_STATUS2__LC_TOTAL_INACTIVE_LANES_MASK                                                         0x0000FFFFL
#define PCIE_LC_STATUS2__LC_TURN_ON_LANE_MASK                                                                 0xFFFF0000L
//PCIE_WPR_CNTL
#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN__SHIFT                                                            0x0
#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN__SHIFT                                                            0x1
#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN__SHIFT                                                            0x2
#define PCIE_WPR_CNTL__WPR_RESET_COR_EN__SHIFT                                                                0x3
#define PCIE_WPR_CNTL__WPR_RESET_REG_EN__SHIFT                                                                0x4
#define PCIE_WPR_CNTL__WPR_RESET_STY_EN__SHIFT                                                                0x5
#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN__SHIFT                                                                0x6
#define PCIE_WPR_CNTL__WPR_RESET_HOT_RST_EN_MASK                                                              0x00000001L
#define PCIE_WPR_CNTL__WPR_RESET_LNK_DWN_EN_MASK                                                              0x00000002L
#define PCIE_WPR_CNTL__WPR_RESET_LNK_DIS_EN_MASK                                                              0x00000004L
#define PCIE_WPR_CNTL__WPR_RESET_COR_EN_MASK                                                                  0x00000008L
#define PCIE_WPR_CNTL__WPR_RESET_REG_EN_MASK                                                                  0x00000010L
#define PCIE_WPR_CNTL__WPR_RESET_STY_EN_MASK                                                                  0x00000020L
#define PCIE_WPR_CNTL__WPR_RESET_PHY_EN_MASK                                                                  0x00000040L
//PCIE_RX_LAST_TLP0
#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0__SHIFT                                                                0x0
#define PCIE_RX_LAST_TLP0__RX_LAST_TLP0_MASK                                                                  0xFFFFFFFFL
//PCIE_RX_LAST_TLP1
#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1__SHIFT                                                                0x0
#define PCIE_RX_LAST_TLP1__RX_LAST_TLP1_MASK                                                                  0xFFFFFFFFL
//PCIE_RX_LAST_TLP2
#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2__SHIFT                                                                0x0
#define PCIE_RX_LAST_TLP2__RX_LAST_TLP2_MASK                                                                  0xFFFFFFFFL
//PCIE_RX_LAST_TLP3
#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3__SHIFT                                                                0x0
#define PCIE_RX_LAST_TLP3__RX_LAST_TLP3_MASK                                                                  0xFFFFFFFFL
//PCIE_TX_LAST_TLP0
#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0__SHIFT                                                                0x0
#define PCIE_TX_LAST_TLP0__TX_LAST_TLP0_MASK                                                                  0xFFFFFFFFL
//PCIE_TX_LAST_TLP1
#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1__SHIFT                                                                0x0
#define PCIE_TX_LAST_TLP1__TX_LAST_TLP1_MASK                                                                  0xFFFFFFFFL
//PCIE_TX_LAST_TLP2
#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2__SHIFT                                                                0x0
#define PCIE_TX_LAST_TLP2__TX_LAST_TLP2_MASK                                                                  0xFFFFFFFFL
//PCIE_TX_LAST_TLP3
#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3__SHIFT                                                                0x0
#define PCIE_TX_LAST_TLP3__TX_LAST_TLP3_MASK                                                                  0xFFFFFFFFL
//PCIE_I2C_REG_ADDR_EXPAND
#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR__SHIFT                                                         0x0
#define PCIE_I2C_REG_ADDR_EXPAND__I2C_REG_ADDR_MASK                                                           0x0001FFFFL
//PCIE_I2C_REG_DATA
#define PCIE_I2C_REG_DATA__I2C_REG_DATA__SHIFT                                                                0x0
#define PCIE_I2C_REG_DATA__I2C_REG_DATA_MASK                                                                  0xFFFFFFFFL
//PCIE_CFG_CNTL
#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                                        0x0
#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                                   0x1
#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                                   0x2
#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                                          0x00000001L
#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                                     0x00000002L
#define PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                                     0x00000004L
//PCIE_LC_PM_CNTL
#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP__SHIFT                                                         0x0
#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP__SHIFT                                                         0x4
#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP__SHIFT                                                         0x8
#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP__SHIFT                                                         0xc
#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP__SHIFT                                                         0x10
#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP__SHIFT                                                         0x14
#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP__SHIFT                                                         0x18
#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP__SHIFT                                                         0x1c
#define PCIE_LC_PM_CNTL__LC_PORT_0_CLKREQB_MAP_MASK                                                           0x0000000FL
#define PCIE_LC_PM_CNTL__LC_PORT_1_CLKREQB_MAP_MASK                                                           0x000000F0L
#define PCIE_LC_PM_CNTL__LC_PORT_2_CLKREQB_MAP_MASK                                                           0x00000F00L
#define PCIE_LC_PM_CNTL__LC_PORT_3_CLKREQB_MAP_MASK                                                           0x0000F000L
#define PCIE_LC_PM_CNTL__LC_PORT_4_CLKREQB_MAP_MASK                                                           0x000F0000L
#define PCIE_LC_PM_CNTL__LC_PORT_5_CLKREQB_MAP_MASK                                                           0x00F00000L
#define PCIE_LC_PM_CNTL__LC_PORT_6_CLKREQB_MAP_MASK                                                           0x0F000000L
#define PCIE_LC_PM_CNTL__LC_PORT_7_CLKREQB_MAP_MASK                                                           0xF0000000L
//PCIE_LC_PORT_ORDER_CNTL
#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN__SHIFT                                                      0x0
#define PCIE_LC_PORT_ORDER_CNTL__LC_PORT_ORDER_EN_MASK                                                        0x00000001L
//PCIE_P_CNTL
#define PCIE_P_CNTL__P_PWRDN_EN__SHIFT                                                                        0x0
#define PCIE_P_CNTL__P_SYMALIGN_MODE__SHIFT                                                                   0x1
#define PCIE_P_CNTL__P_IGNORE_CRC_ERR__SHIFT                                                                  0x4
#define PCIE_P_CNTL__P_IGNORE_LEN_ERR__SHIFT                                                                  0x5
#define PCIE_P_CNTL__P_IGNORE_EDB_ERR__SHIFT                                                                  0x6
#define PCIE_P_CNTL__P_IGNORE_IDL_ERR__SHIFT                                                                  0x7
#define PCIE_P_CNTL__P_IGNORE_TOK_ERR__SHIFT                                                                  0x8
#define PCIE_P_CNTL__P_BLK_LOCK_MODE__SHIFT                                                                   0xc
#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK__SHIFT                                                           0xd
#define PCIE_P_CNTL__P_ELEC_IDLE_MODE__SHIFT                                                                  0xe
#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN__SHIFT                                                               0x10
#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS__SHIFT                                                         0x11
#define PCIE_P_CNTL__P_PWRDN_EN_MASK                                                                          0x00000001L
#define PCIE_P_CNTL__P_SYMALIGN_MODE_MASK                                                                     0x00000002L
#define PCIE_P_CNTL__P_IGNORE_CRC_ERR_MASK                                                                    0x00000010L
#define PCIE_P_CNTL__P_IGNORE_LEN_ERR_MASK                                                                    0x00000020L
#define PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK                                                                    0x00000040L
#define PCIE_P_CNTL__P_IGNORE_IDL_ERR_MASK                                                                    0x00000080L
#define PCIE_P_CNTL__P_IGNORE_TOK_ERR_MASK                                                                    0x00000100L
#define PCIE_P_CNTL__P_BLK_LOCK_MODE_MASK                                                                     0x00001000L
#define PCIE_P_CNTL__P_ALWAYS_USE_FAST_TXCLK_MASK                                                             0x00002000L
#define PCIE_P_CNTL__P_ELEC_IDLE_MODE_MASK                                                                    0x0000C000L
#define PCIE_P_CNTL__DLP_IGNORE_IN_L1_EN_MASK                                                                 0x00010000L
#define PCIE_P_CNTL__ASSERT_DVALID_ON_EI_TRANS_MASK                                                           0x00020000L
//PCIE_P_BUF_STATUS
#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR__SHIFT                                                              0x0
#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR__SHIFT                                                             0x10
#define PCIE_P_BUF_STATUS__P_OVERFLOW_ERR_MASK                                                                0x0000FFFFL
#define PCIE_P_BUF_STATUS__P_UNDERFLOW_ERR_MASK                                                               0xFFFF0000L
//PCIE_P_DECODER_STATUS
#define PCIE_P_DECODER_STATUS__P_DECODE_ERR__SHIFT                                                            0x0
#define PCIE_P_DECODER_STATUS__P_DECODE_ERR_MASK                                                              0x0000FFFFL
//PCIE_P_MISC_STATUS
#define PCIE_P_MISC_STATUS__P_DESKEW_ERR__SHIFT                                                               0x0
#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR__SHIFT                                                            0x10
#define PCIE_P_MISC_STATUS__P_DESKEW_ERR_MASK                                                                 0x000000FFL
#define PCIE_P_MISC_STATUS__P_SYMUNLOCK_ERR_MASK                                                              0xFFFF0000L
//PCIE_P_RCV_L0S_FTS_DET
#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN__SHIFT                                                  0x0
#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX__SHIFT                                                  0x8
#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MIN_MASK                                                    0x000000FFL
#define PCIE_P_RCV_L0S_FTS_DET__P_RCV_L0S_FTS_DET_MAX_MASK                                                    0x0000FF00L
//PCIE_RX_AD
#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO__SHIFT                                                                0x0
#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK__SHIFT                                                                0x1
#define PCIE_RX_AD__RX_SWUS_UR_VDM0__SHIFT                                                                    0x2
#define PCIE_RX_AD__RX_SWUS_DROP_VDM0__SHIFT                                                                  0x3
#define PCIE_RX_AD__RX_SWUS_DROP_VDM1__SHIFT                                                                  0x4
#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS__SHIFT                                                          0x5
#define PCIE_RX_AD__RX_RC_DROP_VDM0__SHIFT                                                                    0x8
#define PCIE_RX_AD__RX_RC_UR_VDM0__SHIFT                                                                      0x9
#define PCIE_RX_AD__RX_RC_DROP_VDM1__SHIFT                                                                    0xa
#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG__SHIFT                                                                  0xb
#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG__SHIFT                                                                  0xc
#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK__SHIFT                                                              0xd
#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS__SHIFT                                                                  0xe
#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE__SHIFT                                                        0xf
#define PCIE_RX_AD__RX_SWUS_DROP_PME_TO_MASK                                                                  0x00000001L
#define PCIE_RX_AD__RX_SWUS_DROP_UNLOCK_MASK                                                                  0x00000002L
#define PCIE_RX_AD__RX_SWUS_UR_VDM0_MASK                                                                      0x00000004L
#define PCIE_RX_AD__RX_SWUS_DROP_VDM0_MASK                                                                    0x00000008L
#define PCIE_RX_AD__RX_SWUS_DROP_VDM1_MASK                                                                    0x00000010L
#define PCIE_RX_AD__RX_SWUS_UR_MSG_PREFIX_DIS_MASK                                                            0x00000020L
#define PCIE_RX_AD__RX_RC_DROP_VDM0_MASK                                                                      0x00000100L
#define PCIE_RX_AD__RX_RC_UR_VDM0_MASK                                                                        0x00000200L
#define PCIE_RX_AD__RX_RC_DROP_VDM1_MASK                                                                      0x00000400L
#define PCIE_RX_AD__RX_RC_UR_SSPL_MSG_MASK                                                                    0x00000800L
#define PCIE_RX_AD__RX_RC_UR_BFRC_MSG_MASK                                                                    0x00001000L
#define PCIE_RX_AD__RX_RC_DROP_PME_TO_ACK_MASK                                                                0x00002000L
#define PCIE_RX_AD__RX_RC_UR_ECRC_DIS_MASK                                                                    0x00004000L
#define PCIE_RX_AD__RX_RC_DROP_CPL_ECRC_FAILURE_MASK                                                          0x00008000L
//PCIE_SDP_CTRL
#define PCIE_SDP_CTRL__SDP_UNIT_ID__SHIFT                                                                     0x0
#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN__SHIFT                                                  0x4
#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN__SHIFT                                                  0x5
#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE__SHIFT                                               0x6
#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS__SHIFT                                                              0x7
#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS__SHIFT                                                            0x8
#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS__SHIFT                                                       0x9
#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS__SHIFT                                                        0xa
#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING__SHIFT                                                         0xb
#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS__SHIFT                                                     0xc
#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN__SHIFT                                                    0xd
#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL__SHIFT                                             0xe
#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS__SHIFT                                                   0xf
#define PCIE_SDP_CTRL__SDP_UNIT_ID_MASK                                                                       0x0000000FL
#define PCIE_SDP_CTRL__CI_SLV_REQR_FULL_DISCONNECT_EN_MASK                                                    0x00000010L
#define PCIE_SDP_CTRL__CI_SLV_REQR_PART_DISCONNECT_EN_MASK                                                    0x00000020L
#define PCIE_SDP_CTRL__CI_MSTSDP_CLKGATE_ONESIDED_ENABLE_MASK                                                 0x00000040L
#define PCIE_SDP_CTRL__TX_RC_TPH_PRIV_DIS_MASK                                                                0x00000080L
#define PCIE_SDP_CTRL__TX_SWUS_TPH_PRIV_DIS_MASK                                                              0x00000100L
#define PCIE_SDP_CTRL__CI_SLAVE_TAG_STEALING_DIS_MASK                                                         0x00000200L
#define PCIE_SDP_CTRL__SLAVE_PREFIX_PRELOAD_DIS_MASK                                                          0x00000400L
#define PCIE_SDP_CTRL__CI_DISABLE_LTR_DROPPING_MASK                                                           0x00000800L
#define PCIE_SDP_CTRL__RX_SWUS_SIDEBAND_CPLHDR_DIS_MASK                                                       0x00001000L
#define PCIE_SDP_CTRL__CI_MST_MEMR_RD_NONCONT_BE_EN_MASK                                                      0x00002000L
#define PCIE_SDP_CTRL__CI_MSTSDP_DISCONNECT_RSP_ON_PARTIAL_MASK                                               0x00004000L
#define PCIE_SDP_CTRL__CI_SWUS_RCVD_ERR_HANDLING_DIS_MASK                                                     0x00008000L
//PCIE_SDP_SWUS_SLV_ATTR_CTRL
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR__SHIFT                                     0x0
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD__SHIFT                                     0x2
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC__SHIFT                                    0x4
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR__SHIFT                                    0x6
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD__SHIFT                                    0x8
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC__SHIFT                                   0xa
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR__SHIFT                                    0xc
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD__SHIFT                                    0xe
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC__SHIFT                                   0x10
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMWR_MASK                                       0x00000003L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_MEMRD_MASK                                       0x0000000CL
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_RO_OVERRIDE_ATOMIC_MASK                                      0x00000030L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMWR_MASK                                      0x000000C0L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_MEMRD_MASK                                      0x00000300L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_SNR_OVERRIDE_ATOMIC_MASK                                     0x00000C00L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMWR_MASK                                      0x00003000L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_MEMRD_MASK                                      0x0000C000L
#define PCIE_SDP_SWUS_SLV_ATTR_CTRL__CI_SWUS_SLV_IDO_OVERRIDE_ATOMIC_MASK                                     0x00030000L
//PCIE_PERF_COUNT_CNTL
#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN__SHIFT                                                          0x0
#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR__SHIFT                                                         0x1
#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET__SHIFT                                                       0x2
#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_EN_MASK                                                            0x00000001L
#define PCIE_PERF_COUNT_CNTL__GLOBAL_SHADOW_WR_MASK                                                           0x00000002L
#define PCIE_PERF_COUNT_CNTL__GLOBAL_COUNT_RESET_MASK                                                         0x00000004L
//PCIE_PERF_CNTL_TXCLK
#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL__SHIFT                                                               0x0
#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL__SHIFT                                                               0x8
#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER__SHIFT                                                           0x10
#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER__SHIFT                                                           0x18
#define PCIE_PERF_CNTL_TXCLK__EVENT0_SEL_MASK                                                                 0x000000FFL
#define PCIE_PERF_CNTL_TXCLK__EVENT1_SEL_MASK                                                                 0x0000FF00L
#define PCIE_PERF_CNTL_TXCLK__COUNTER0_UPPER_MASK                                                             0x00FF0000L
#define PCIE_PERF_CNTL_TXCLK__COUNTER1_UPPER_MASK                                                             0xFF000000L
//PCIE_PERF_COUNT0_TXCLK
#define PCIE_PERF_COUNT0_TXCLK__COUNTER0__SHIFT                                                               0x0
#define PCIE_PERF_COUNT0_TXCLK__COUNTER0_MASK                                                                 0xFFFFFFFFL
//PCIE_PERF_COUNT1_TXCLK
#define PCIE_PERF_COUNT1_TXCLK__COUNTER1__SHIFT                                                               0x0
#define PCIE_PERF_COUNT1_TXCLK__COUNTER1_MASK                                                                 0xFFFFFFFFL
//PCIE_PERF_CNTL_MST_R_CLK
#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL__SHIFT                                                           0x0
#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL__SHIFT                                                           0x8
#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER__SHIFT                                                       0x10
#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER__SHIFT                                                       0x18
#define PCIE_PERF_CNTL_MST_R_CLK__EVENT0_SEL_MASK                                                             0x000000FFL
#define PCIE_PERF_CNTL_MST_R_CLK__EVENT1_SEL_MASK                                                             0x0000FF00L
#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER0_UPPER_MASK                                                         0x00FF0000L
#define PCIE_PERF_CNTL_MST_R_CLK__COUNTER1_UPPER_MASK                                                         0xFF000000L
//PCIE_PERF_COUNT0_MST_R_CLK
#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0__SHIFT                                                           0x0
#define PCIE_PERF_COUNT0_MST_R_CLK__COUNTER0_MASK                                                             0xFFFFFFFFL
//PCIE_PERF_COUNT1_MST_R_CLK
#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1__SHIFT                                                           0x0
#define PCIE_PERF_COUNT1_MST_R_CLK__COUNTER1_MASK                                                             0xFFFFFFFFL
//PCIE_PERF_CNTL_MST_C_CLK
#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL__SHIFT                                                           0x0
#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL__SHIFT                                                           0x8
#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER__SHIFT                                                       0x10
#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER__SHIFT                                                       0x18
#define PCIE_PERF_CNTL_MST_C_CLK__EVENT0_SEL_MASK                                                             0x000000FFL
#define PCIE_PERF_CNTL_MST_C_CLK__EVENT1_SEL_MASK                                                             0x0000FF00L
#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER0_UPPER_MASK                                                         0x00FF0000L
#define PCIE_PERF_CNTL_MST_C_CLK__COUNTER1_UPPER_MASK                                                         0xFF000000L
//PCIE_PERF_COUNT0_MST_C_CLK
#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0__SHIFT                                                           0x0
#define PCIE_PERF_COUNT0_MST_C_CLK__COUNTER0_MASK                                                             0xFFFFFFFFL
//PCIE_PERF_COUNT1_MST_C_CLK
#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1__SHIFT                                                           0x0
#define PCIE_PERF_COUNT1_MST_C_CLK__COUNTER1_MASK                                                             0xFFFFFFFFL
//PCIE_PERF_CNTL_SLV_R_CLK
#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL__SHIFT                                                           0x0
#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL__SHIFT                                                           0x8
#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER__SHIFT                                                       0x10
#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER__SHIFT                                                       0x18
#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT0_SEL_MASK                                                             0x000000FFL
#define PCIE_PERF_CNTL_SLV_R_CLK__EVENT1_SEL_MASK                                                             0x0000FF00L
#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER0_UPPER_MASK                                                         0x00FF0000L
#define PCIE_PERF_CNTL_SLV_R_CLK__COUNTER1_UPPER_MASK                                                         0xFF000000L
//PCIE_PERF_COUNT0_SLV_R_CLK
#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0__SHIFT                                                           0x0
#define PCIE_PERF_COUNT0_SLV_R_CLK__COUNTER0_MASK                                                             0xFFFFFFFFL
//PCIE_PERF_COUNT1_SLV_R_CLK
#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1__SHIFT                                                           0x0
#define PCIE_PERF_COUNT1_SLV_R_CLK__COUNTER1_MASK                                                             0xFFFFFFFFL
//PCIE_PERF_CNTL_SLV_S_C_CLK
#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL__SHIFT                                                         0x0
#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL__SHIFT                                                         0x8
#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER__SHIFT                                                     0x10
#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER__SHIFT                                                     0x18
#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT0_SEL_MASK                                                           0x000000FFL
#define PCIE_PERF_CNTL_SLV_S_C_CLK__EVENT1_SEL_MASK                                                           0x0000FF00L
#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER0_UPPER_MASK                                                       0x00FF0000L
#define PCIE_PERF_CNTL_SLV_S_C_CLK__COUNTER1_UPPER_MASK                                                       0xFF000000L
//PCIE_PERF_COUNT0_SLV_S_C_CLK
#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0__SHIFT                                                         0x0
#define PCIE_PERF_COUNT0_SLV_S_C_CLK__COUNTER0_MASK                                                           0xFFFFFFFFL
//PCIE_PERF_COUNT1_SLV_S_C_CLK
#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1__SHIFT                                                         0x0
#define PCIE_PERF_COUNT1_SLV_S_C_CLK__COUNTER1_MASK                                                           0xFFFFFFFFL
//PCIE_PERF_CNTL_SLV_NS_C_CLK
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL__SHIFT                                                        0x0
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL__SHIFT                                                        0x8
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER__SHIFT                                                    0x10
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER__SHIFT                                                    0x18
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT0_SEL_MASK                                                          0x000000FFL
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__EVENT1_SEL_MASK                                                          0x0000FF00L
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER0_UPPER_MASK                                                      0x00FF0000L
#define PCIE_PERF_CNTL_SLV_NS_C_CLK__COUNTER1_UPPER_MASK                                                      0xFF000000L
//PCIE_PERF_COUNT0_SLV_NS_C_CLK
#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0__SHIFT                                                        0x0
#define PCIE_PERF_COUNT0_SLV_NS_C_CLK__COUNTER0_MASK                                                          0xFFFFFFFFL
//PCIE_PERF_COUNT1_SLV_NS_C_CLK
#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1__SHIFT                                                        0x0
#define PCIE_PERF_COUNT1_SLV_NS_C_CLK__COUNTER1_MASK                                                          0xFFFFFFFFL
//PCIE_PERF_CNTL_EVENT0_PORT_SEL
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK__SHIFT                                           0x0
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK__SHIFT                                       0x4
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK__SHIFT                                       0x8
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK__SHIFT                                       0xc
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK__SHIFT                                     0x10
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK__SHIFT                                    0x14
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2__SHIFT                                          0x18
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK_MASK                                             0x0000000FL
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_R_CLK_MASK                                         0x000000F0L
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_MST_C_CLK_MASK                                         0x00000F00L
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_R_CLK_MASK                                         0x0000F000L
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_S_C_CLK_MASK                                       0x000F0000L
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_SLV_NS_C_CLK_MASK                                      0x00F00000L
#define PCIE_PERF_CNTL_EVENT0_PORT_SEL__PERF0_PORT_SEL_TXCLK2_MASK                                            0x0F000000L
//PCIE_PERF_CNTL_EVENT1_PORT_SEL
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK__SHIFT                                           0x0
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK__SHIFT                                       0x4
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK__SHIFT                                       0x8
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK__SHIFT                                       0xc
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK__SHIFT                                     0x10
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK__SHIFT                                    0x14
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2__SHIFT                                          0x18
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK_MASK                                             0x0000000FL
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_R_CLK_MASK                                         0x000000F0L
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_MST_C_CLK_MASK                                         0x00000F00L
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_R_CLK_MASK                                         0x0000F000L
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_S_C_CLK_MASK                                       0x000F0000L
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_SLV_NS_C_CLK_MASK                                      0x00F00000L
#define PCIE_PERF_CNTL_EVENT1_PORT_SEL__PERF1_PORT_SEL_TXCLK2_MASK                                            0x0F000000L
//PCIE_PERF_CNTL_TXCLK2
#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL__SHIFT                                                              0x0
#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL__SHIFT                                                              0x8
#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER__SHIFT                                                          0x10
#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER__SHIFT                                                          0x18
#define PCIE_PERF_CNTL_TXCLK2__EVENT0_SEL_MASK                                                                0x000000FFL
#define PCIE_PERF_CNTL_TXCLK2__EVENT1_SEL_MASK                                                                0x0000FF00L
#define PCIE_PERF_CNTL_TXCLK2__COUNTER0_UPPER_MASK                                                            0x00FF0000L
#define PCIE_PERF_CNTL_TXCLK2__COUNTER1_UPPER_MASK                                                            0xFF000000L
//PCIE_PERF_COUNT0_TXCLK2
#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0__SHIFT                                                              0x0
#define PCIE_PERF_COUNT0_TXCLK2__COUNTER0_MASK                                                                0xFFFFFFFFL
//PCIE_PERF_COUNT1_TXCLK2
#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1__SHIFT                                                              0x0
#define PCIE_PERF_COUNT1_TXCLK2__COUNTER1_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_CLR
#define PCIE_PRBS_CLR__PRBS_CLR__SHIFT                                                                        0x0
#define PCIE_PRBS_CLR__PRBS_POLARITY_EN__SHIFT                                                                0x18
#define PCIE_PRBS_CLR__PRBS_CLR_MASK                                                                          0x0000FFFFL
#define PCIE_PRBS_CLR__PRBS_POLARITY_EN_MASK                                                                  0x01000000L
//PCIE_PRBS_STATUS1
#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT__SHIFT                                                                0x0
#define PCIE_PRBS_STATUS1__PRBS_LOCKED__SHIFT                                                                 0x10
#define PCIE_PRBS_STATUS1__PRBS_ERRSTAT_MASK                                                                  0x0000FFFFL
#define PCIE_PRBS_STATUS1__PRBS_LOCKED_MASK                                                                   0xFFFF0000L
//PCIE_PRBS_STATUS2
#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE__SHIFT                                                            0x0
#define PCIE_PRBS_STATUS2__PRBS_BITCNT_DONE_MASK                                                              0x0000FFFFL
//PCIE_PRBS_FREERUN
#define PCIE_PRBS_FREERUN__PRBS_FREERUN__SHIFT                                                                0x0
#define PCIE_PRBS_FREERUN__PRBS_FREERUN_MASK                                                                  0x0000FFFFL
//PCIE_PRBS_MISC
#define PCIE_PRBS_MISC__PRBS_EN__SHIFT                                                                        0x0
#define PCIE_PRBS_MISC__PRBS_TEST_MODE__SHIFT                                                                 0x1
#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE__SHIFT                                                       0x4
#define PCIE_PRBS_MISC__PRBS_8BIT_SEL__SHIFT                                                                  0x5
#define PCIE_PRBS_MISC__PRBS_COMMA_NUM__SHIFT                                                                 0x6
#define PCIE_PRBS_MISC__PRBS_LOCK_CNT__SHIFT                                                                  0x8
#define PCIE_PRBS_MISC__PRBS_DATA_RATE__SHIFT                                                                 0xe
#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK__SHIFT                                                              0x10
#define PCIE_PRBS_MISC__PRBS_EN_MASK                                                                          0x00000001L
#define PCIE_PRBS_MISC__PRBS_TEST_MODE_MASK                                                                   0x0000000EL
#define PCIE_PRBS_MISC__PRBS_USER_PATTERN_TOGGLE_MASK                                                         0x00000010L
#define PCIE_PRBS_MISC__PRBS_8BIT_SEL_MASK                                                                    0x00000020L
#define PCIE_PRBS_MISC__PRBS_COMMA_NUM_MASK                                                                   0x000000C0L
#define PCIE_PRBS_MISC__PRBS_LOCK_CNT_MASK                                                                    0x00001F00L
#define PCIE_PRBS_MISC__PRBS_DATA_RATE_MASK                                                                   0x0000C000L
#define PCIE_PRBS_MISC__PRBS_CHK_ERR_MASK_MASK                                                                0xFFFF0000L
//PCIE_PRBS_USER_PATTERN
#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN__SHIFT                                                      0x0
#define PCIE_PRBS_USER_PATTERN__PRBS_USER_PATTERN_MASK                                                        0x3FFFFFFFL
//PCIE_PRBS_LO_BITCNT
#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT__SHIFT                                                            0x0
#define PCIE_PRBS_LO_BITCNT__PRBS_LO_BITCNT_MASK                                                              0xFFFFFFFFL
//PCIE_PRBS_HI_BITCNT
#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT__SHIFT                                                            0x0
#define PCIE_PRBS_HI_BITCNT__PRBS_HI_BITCNT_MASK                                                              0x000000FFL
//PCIE_PRBS_ERRCNT_0
#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_0__PRBS_ERRCNT_0_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_1
#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_1__PRBS_ERRCNT_1_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_2
#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_2__PRBS_ERRCNT_2_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_3
#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_3__PRBS_ERRCNT_3_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_4
#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_4__PRBS_ERRCNT_4_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_5
#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_5__PRBS_ERRCNT_5_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_6
#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_6__PRBS_ERRCNT_6_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_7
#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_7__PRBS_ERRCNT_7_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_8
#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_8__PRBS_ERRCNT_8_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_9
#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9__SHIFT                                                              0x0
#define PCIE_PRBS_ERRCNT_9__PRBS_ERRCNT_9_MASK                                                                0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_10
#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10__SHIFT                                                            0x0
#define PCIE_PRBS_ERRCNT_10__PRBS_ERRCNT_10_MASK                                                              0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_11
#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11__SHIFT                                                            0x0
#define PCIE_PRBS_ERRCNT_11__PRBS_ERRCNT_11_MASK                                                              0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_12
#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12__SHIFT                                                            0x0
#define PCIE_PRBS_ERRCNT_12__PRBS_ERRCNT_12_MASK                                                              0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_13
#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13__SHIFT                                                            0x0
#define PCIE_PRBS_ERRCNT_13__PRBS_ERRCNT_13_MASK                                                              0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_14
#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14__SHIFT                                                            0x0
#define PCIE_PRBS_ERRCNT_14__PRBS_ERRCNT_14_MASK                                                              0xFFFFFFFFL
//PCIE_PRBS_ERRCNT_15
#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15__SHIFT                                                            0x0
#define PCIE_PRBS_ERRCNT_15__PRBS_ERRCNT_15_MASK                                                              0xFFFFFFFFL
//SWRST_COMMAND_STATUS
#define SWRST_COMMAND_STATUS__RECONFIGURE__SHIFT                                                              0x0
#define SWRST_COMMAND_STATUS__ATOMIC_RESET__SHIFT                                                             0x1
#define SWRST_COMMAND_STATUS__RESET_COMPLETE__SHIFT                                                           0x10
#define SWRST_COMMAND_STATUS__WAIT_STATE__SHIFT                                                               0x11
#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET__SHIFT                                                          0x18
#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY__SHIFT                                                 0x19
#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB__SHIFT                                                0x1a
#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET__SHIFT                                                          0x1b
#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY__SHIFT                                                 0x1c
#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET__SHIFT                                                0x1d
#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE__SHIFT                                             0x1e
#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN__SHIFT                                                0x1f
#define SWRST_COMMAND_STATUS__RECONFIGURE_MASK                                                                0x00000001L
#define SWRST_COMMAND_STATUS__ATOMIC_RESET_MASK                                                               0x00000002L
#define SWRST_COMMAND_STATUS__RESET_COMPLETE_MASK                                                             0x00010000L
#define SWRST_COMMAND_STATUS__WAIT_STATE_MASK                                                                 0x00020000L
#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_MASK                                                            0x01000000L
#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_CFG_ONLY_MASK                                                   0x02000000L
#define SWRST_COMMAND_STATUS__SWUS_LINK_RESET_PHY_CALIB_MASK                                                  0x04000000L
#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_MASK                                                            0x08000000L
#define SWRST_COMMAND_STATUS__SWDS_LINK_RESET_CFG_ONLY_MASK                                                   0x10000000L
#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_HOT_RESET_MASK                                                  0x20000000L
#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DISABLE_MASK                                               0x40000000L
#define SWRST_COMMAND_STATUS__LINK_RESET_TYPE_LINK_DOWN_MASK                                                  0x80000000L
//SWRST_GENERAL_CONTROL
#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN__SHIFT                                                          0x0
#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN__SHIFT                                                         0x1
#define SWRST_GENERAL_CONTROL__RESET_PERIOD__SHIFT                                                            0x2
#define SWRST_GENERAL_CONTROL__WAIT_LINKUP__SHIFT                                                             0x8
#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE__SHIFT                                                           0x9
#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE__SHIFT                                                           0xa
#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE__SHIFT                                                        0xc
#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD__SHIFT                                                         0x11
#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT                                          0x18
#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET__SHIFT                                                        0x19
#define SWRST_GENERAL_CONTROL__RECONFIGURE_EN_MASK                                                            0x00000001L
#define SWRST_GENERAL_CONTROL__ATOMIC_RESET_EN_MASK                                                           0x00000002L
#define SWRST_GENERAL_CONTROL__RESET_PERIOD_MASK                                                              0x0000001CL
#define SWRST_GENERAL_CONTROL__WAIT_LINKUP_MASK                                                               0x00000100L
#define SWRST_GENERAL_CONTROL__FORCE_REGIDLE_MASK                                                             0x00000200L
#define SWRST_GENERAL_CONTROL__BLOCK_ON_IDLE_MASK                                                             0x00000400L
#define SWRST_GENERAL_CONTROL__CONFIG_XFER_MODE_MASK                                                          0x00001000L
#define SWRST_GENERAL_CONTROL__BYPASS_PCS_HOLD_MASK                                                           0x00020000L
#define SWRST_GENERAL_CONTROL__MP1_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK                                            0x01000000L
#define SWRST_GENERAL_CONTROL__IGNORE_SDP_RESET_MASK                                                          0x02000000L
//SWRST_COMMAND_0
#define SWRST_COMMAND_0__PORT0_COR_RESET__SHIFT                                                               0x0
#define SWRST_COMMAND_0__PORT0_CFG_RESET__SHIFT                                                               0x8
#define SWRST_COMMAND_0__PORT1_CFG_RESET__SHIFT                                                               0x9
#define SWRST_COMMAND_0__PORT2_CFG_RESET__SHIFT                                                               0xa
#define SWRST_COMMAND_0__PORT3_CFG_RESET__SHIFT                                                               0xb
#define SWRST_COMMAND_0__PORT4_CFG_RESET__SHIFT                                                               0xc
#define SWRST_COMMAND_0__PORT5_CFG_RESET__SHIFT                                                               0xd
#define SWRST_COMMAND_0__PORT6_CFG_RESET__SHIFT                                                               0xe
#define SWRST_COMMAND_0__PORT7_CFG_RESET__SHIFT                                                               0xf
#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET__SHIFT                                                             0x18
#define SWRST_COMMAND_0__BIF0_CALIB_RESET__SHIFT                                                              0x19
#define SWRST_COMMAND_0__BIF0_CORE_RESET__SHIFT                                                               0x1a
#define SWRST_COMMAND_0__BIF0_REGISTER_RESET__SHIFT                                                           0x1b
#define SWRST_COMMAND_0__BIF0_PHY_RESET__SHIFT                                                                0x1c
#define SWRST_COMMAND_0__BIF0_STICKY_RESET__SHIFT                                                             0x1d
#define SWRST_COMMAND_0__BIF0_CONFIG_RESET__SHIFT                                                             0x1e
#define SWRST_COMMAND_0__PORT0_COR_RESET_MASK                                                                 0x00000001L
#define SWRST_COMMAND_0__PORT0_CFG_RESET_MASK                                                                 0x00000100L
#define SWRST_COMMAND_0__PORT1_CFG_RESET_MASK                                                                 0x00000200L
#define SWRST_COMMAND_0__PORT2_CFG_RESET_MASK                                                                 0x00000400L
#define SWRST_COMMAND_0__PORT3_CFG_RESET_MASK                                                                 0x00000800L
#define SWRST_COMMAND_0__PORT4_CFG_RESET_MASK                                                                 0x00001000L
#define SWRST_COMMAND_0__PORT5_CFG_RESET_MASK                                                                 0x00002000L
#define SWRST_COMMAND_0__PORT6_CFG_RESET_MASK                                                                 0x00004000L
#define SWRST_COMMAND_0__PORT7_CFG_RESET_MASK                                                                 0x00008000L
#define SWRST_COMMAND_0__BIF0_GLOBAL_RESET_MASK                                                               0x01000000L
#define SWRST_COMMAND_0__BIF0_CALIB_RESET_MASK                                                                0x02000000L
#define SWRST_COMMAND_0__BIF0_CORE_RESET_MASK                                                                 0x04000000L
#define SWRST_COMMAND_0__BIF0_REGISTER_RESET_MASK                                                             0x08000000L
#define SWRST_COMMAND_0__BIF0_PHY_RESET_MASK                                                                  0x10000000L
#define SWRST_COMMAND_0__BIF0_STICKY_RESET_MASK                                                               0x20000000L
#define SWRST_COMMAND_0__BIF0_CONFIG_RESET_MASK                                                               0x40000000L
//SWRST_COMMAND_1
#define SWRST_COMMAND_1__RESETPCS0__SHIFT                                                                     0x0
#define SWRST_COMMAND_1__RESETPCS1__SHIFT                                                                     0x1
#define SWRST_COMMAND_1__RESETPCS2__SHIFT                                                                     0x2
#define SWRST_COMMAND_1__RESETPCS3__SHIFT                                                                     0x3
#define SWRST_COMMAND_1__RESETPCS4__SHIFT                                                                     0x4
#define SWRST_COMMAND_1__RESETPCS5__SHIFT                                                                     0x5
#define SWRST_COMMAND_1__RESETPCS6__SHIFT                                                                     0x6
#define SWRST_COMMAND_1__RESETPCS7__SHIFT                                                                     0x7
#define SWRST_COMMAND_1__RESETPCS8__SHIFT                                                                     0x8
#define SWRST_COMMAND_1__RESETPCS9__SHIFT                                                                     0x9
#define SWRST_COMMAND_1__RESETPCS10__SHIFT                                                                    0xa
#define SWRST_COMMAND_1__RESETPCS11__SHIFT                                                                    0xb
#define SWRST_COMMAND_1__RESETPCS12__SHIFT                                                                    0xc
#define SWRST_COMMAND_1__RESETPCS13__SHIFT                                                                    0xd
#define SWRST_COMMAND_1__RESETPCS14__SHIFT                                                                    0xe
#define SWRST_COMMAND_1__RESETPCS15__SHIFT                                                                    0xf
#define SWRST_COMMAND_1__SWITCHCLK__SHIFT                                                                     0x15
#define SWRST_COMMAND_1__RESETAXIMST__SHIFT                                                                   0x16
#define SWRST_COMMAND_1__RESETAXISLV__SHIFT                                                                   0x17
#define SWRST_COMMAND_1__RESETAXIINT__SHIFT                                                                   0x18
#define SWRST_COMMAND_1__RESETPCFG__SHIFT                                                                     0x19
#define SWRST_COMMAND_1__RESETLNCT__SHIFT                                                                     0x1a
#define SWRST_COMMAND_1__RESETMNTR__SHIFT                                                                     0x1b
#define SWRST_COMMAND_1__RESETHLTR__SHIFT                                                                     0x1c
#define SWRST_COMMAND_1__RESETCPM__SHIFT                                                                      0x1d
#define SWRST_COMMAND_1__RESETPHY0__SHIFT                                                                     0x1e
#define SWRST_COMMAND_1__TOGGLESTRAP__SHIFT                                                                   0x1f
#define SWRST_COMMAND_1__RESETPCS0_MASK                                                                       0x00000001L
#define SWRST_COMMAND_1__RESETPCS1_MASK                                                                       0x00000002L
#define SWRST_COMMAND_1__RESETPCS2_MASK                                                                       0x00000004L
#define SWRST_COMMAND_1__RESETPCS3_MASK                                                                       0x00000008L
#define SWRST_COMMAND_1__RESETPCS4_MASK                                                                       0x00000010L
#define SWRST_COMMAND_1__RESETPCS5_MASK                                                                       0x00000020L
#define SWRST_COMMAND_1__RESETPCS6_MASK                                                                       0x00000040L
#define SWRST_COMMAND_1__RESETPCS7_MASK                                                                       0x00000080L
#define SWRST_COMMAND_1__RESETPCS8_MASK                                                                       0x00000100L
#define SWRST_COMMAND_1__RESETPCS9_MASK                                                                       0x00000200L
#define SWRST_COMMAND_1__RESETPCS10_MASK                                                                      0x00000400L
#define SWRST_COMMAND_1__RESETPCS11_MASK                                                                      0x00000800L
#define SWRST_COMMAND_1__RESETPCS12_MASK                                                                      0x00001000L
#define SWRST_COMMAND_1__RESETPCS13_MASK                                                                      0x00002000L
#define SWRST_COMMAND_1__RESETPCS14_MASK                                                                      0x00004000L
#define SWRST_COMMAND_1__RESETPCS15_MASK                                                                      0x00008000L
#define SWRST_COMMAND_1__SWITCHCLK_MASK                                                                       0x00200000L
#define SWRST_COMMAND_1__RESETAXIMST_MASK                                                                     0x00400000L
#define SWRST_COMMAND_1__RESETAXISLV_MASK                                                                     0x00800000L
#define SWRST_COMMAND_1__RESETAXIINT_MASK                                                                     0x01000000L
#define SWRST_COMMAND_1__RESETPCFG_MASK                                                                       0x02000000L
#define SWRST_COMMAND_1__RESETLNCT_MASK                                                                       0x04000000L
#define SWRST_COMMAND_1__RESETMNTR_MASK                                                                       0x08000000L
#define SWRST_COMMAND_1__RESETHLTR_MASK                                                                       0x10000000L
#define SWRST_COMMAND_1__RESETCPM_MASK                                                                        0x20000000L
#define SWRST_COMMAND_1__RESETPHY0_MASK                                                                       0x40000000L
#define SWRST_COMMAND_1__TOGGLESTRAP_MASK                                                                     0x80000000L
//SWRST_CONTROL_0
#define SWRST_CONTROL_0__PORT0_COR_RCEN__SHIFT                                                                0x0
#define SWRST_CONTROL_0__PORT0_CFG_RCEN__SHIFT                                                                0x8
#define SWRST_CONTROL_0__PORT1_CFG_RCEN__SHIFT                                                                0x9
#define SWRST_CONTROL_0__PORT2_CFG_RCEN__SHIFT                                                                0xa
#define SWRST_CONTROL_0__PORT3_CFG_RCEN__SHIFT                                                                0xb
#define SWRST_CONTROL_0__PORT4_CFG_RCEN__SHIFT                                                                0xc
#define SWRST_CONTROL_0__PORT5_CFG_RCEN__SHIFT                                                                0xd
#define SWRST_CONTROL_0__PORT6_CFG_RCEN__SHIFT                                                                0xe
#define SWRST_CONTROL_0__PORT7_CFG_RCEN__SHIFT                                                                0xf
#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN__SHIFT                                                         0x18
#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN__SHIFT                                                          0x19
#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN__SHIFT                                                           0x1a
#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN__SHIFT                                                       0x1b
#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN__SHIFT                                                            0x1c
#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN__SHIFT                                                         0x1d
#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN__SHIFT                                                         0x1e
#define SWRST_CONTROL_0__PORT0_COR_RCEN_MASK                                                                  0x00000001L
#define SWRST_CONTROL_0__PORT0_CFG_RCEN_MASK                                                                  0x00000100L
#define SWRST_CONTROL_0__PORT1_CFG_RCEN_MASK                                                                  0x00000200L
#define SWRST_CONTROL_0__PORT2_CFG_RCEN_MASK                                                                  0x00000400L
#define SWRST_CONTROL_0__PORT3_CFG_RCEN_MASK                                                                  0x00000800L
#define SWRST_CONTROL_0__PORT4_CFG_RCEN_MASK                                                                  0x00001000L
#define SWRST_CONTROL_0__PORT5_CFG_RCEN_MASK                                                                  0x00002000L
#define SWRST_CONTROL_0__PORT6_CFG_RCEN_MASK                                                                  0x00004000L
#define SWRST_CONTROL_0__PORT7_CFG_RCEN_MASK                                                                  0x00008000L
#define SWRST_CONTROL_0__BIF0_GLOBAL_RESETRCEN_MASK                                                           0x01000000L
#define SWRST_CONTROL_0__BIF0_CALIB_RESETRCEN_MASK                                                            0x02000000L
#define SWRST_CONTROL_0__BIF0_CORE_RESETRCEN_MASK                                                             0x04000000L
#define SWRST_CONTROL_0__BIF0_REGISTER_RESETRCEN_MASK                                                         0x08000000L
#define SWRST_CONTROL_0__BIF0_PHY_RESETRCEN_MASK                                                              0x10000000L
#define SWRST_CONTROL_0__BIF0_STICKY_RESETRCEN_MASK                                                           0x20000000L
#define SWRST_CONTROL_0__BIF0_CONFIG_RESETRCEN_MASK                                                           0x40000000L
//SWRST_CONTROL_1
#define SWRST_CONTROL_1__PCSRESET0_RCEN__SHIFT                                                                0x0
#define SWRST_CONTROL_1__PCSRESET1_RCEN__SHIFT                                                                0x1
#define SWRST_CONTROL_1__PCSRESET2_RCEN__SHIFT                                                                0x2
#define SWRST_CONTROL_1__PCSRESET3_RCEN__SHIFT                                                                0x3
#define SWRST_CONTROL_1__PCSRESET4_RCEN__SHIFT                                                                0x4
#define SWRST_CONTROL_1__PCSRESET5_RCEN__SHIFT                                                                0x5
#define SWRST_CONTROL_1__PCSRESET6_RCEN__SHIFT                                                                0x6
#define SWRST_CONTROL_1__PCSRESET7_RCEN__SHIFT                                                                0x7
#define SWRST_CONTROL_1__PCSRESET8_RCEN__SHIFT                                                                0x8
#define SWRST_CONTROL_1__PCSRESET9_RCEN__SHIFT                                                                0x9
#define SWRST_CONTROL_1__PCSRESET10_RCEN__SHIFT                                                               0xa
#define SWRST_CONTROL_1__PCSRESET11_RCEN__SHIFT                                                               0xb
#define SWRST_CONTROL_1__PCSRESET12_RCEN__SHIFT                                                               0xc
#define SWRST_CONTROL_1__PCSRESET13_RCEN__SHIFT                                                               0xd
#define SWRST_CONTROL_1__PCSRESET14_RCEN__SHIFT                                                               0xe
#define SWRST_CONTROL_1__PCSRESET15_RCEN__SHIFT                                                               0xf
#define SWRST_CONTROL_1__SWITCHCLK_RCEN__SHIFT                                                                0x15
#define SWRST_CONTROL_1__RESETAXIMST_RCEN__SHIFT                                                              0x16
#define SWRST_CONTROL_1__RESETAXISLV_RCEN__SHIFT                                                              0x17
#define SWRST_CONTROL_1__RESETAXIINT_RCEN__SHIFT                                                              0x18
#define SWRST_CONTROL_1__RESETPCFG_RCEN__SHIFT                                                                0x19
#define SWRST_CONTROL_1__RESETLNCT_RCEN__SHIFT                                                                0x1a
#define SWRST_CONTROL_1__RESETMNTR_RCEN__SHIFT                                                                0x1b
#define SWRST_CONTROL_1__RESETHLTR_RCEN__SHIFT                                                                0x1c
#define SWRST_CONTROL_1__RESETCPM_RCEN__SHIFT                                                                 0x1d
#define SWRST_CONTROL_1__RESETPHY0_RCEN__SHIFT                                                                0x1e
#define SWRST_CONTROL_1__STRAPVLD_RCEN__SHIFT                                                                 0x1f
#define SWRST_CONTROL_1__PCSRESET0_RCEN_MASK                                                                  0x00000001L
#define SWRST_CONTROL_1__PCSRESET1_RCEN_MASK                                                                  0x00000002L
#define SWRST_CONTROL_1__PCSRESET2_RCEN_MASK                                                                  0x00000004L
#define SWRST_CONTROL_1__PCSRESET3_RCEN_MASK                                                                  0x00000008L
#define SWRST_CONTROL_1__PCSRESET4_RCEN_MASK                                                                  0x00000010L
#define SWRST_CONTROL_1__PCSRESET5_RCEN_MASK                                                                  0x00000020L
#define SWRST_CONTROL_1__PCSRESET6_RCEN_MASK                                                                  0x00000040L
#define SWRST_CONTROL_1__PCSRESET7_RCEN_MASK                                                                  0x00000080L
#define SWRST_CONTROL_1__PCSRESET8_RCEN_MASK                                                                  0x00000100L
#define SWRST_CONTROL_1__PCSRESET9_RCEN_MASK                                                                  0x00000200L
#define SWRST_CONTROL_1__PCSRESET10_RCEN_MASK                                                                 0x00000400L
#define SWRST_CONTROL_1__PCSRESET11_RCEN_MASK                                                                 0x00000800L
#define SWRST_CONTROL_1__PCSRESET12_RCEN_MASK                                                                 0x00001000L
#define SWRST_CONTROL_1__PCSRESET13_RCEN_MASK                                                                 0x00002000L
#define SWRST_CONTROL_1__PCSRESET14_RCEN_MASK                                                                 0x00004000L
#define SWRST_CONTROL_1__PCSRESET15_RCEN_MASK                                                                 0x00008000L
#define SWRST_CONTROL_1__SWITCHCLK_RCEN_MASK                                                                  0x00200000L
#define SWRST_CONTROL_1__RESETAXIMST_RCEN_MASK                                                                0x00400000L
#define SWRST_CONTROL_1__RESETAXISLV_RCEN_MASK                                                                0x00800000L
#define SWRST_CONTROL_1__RESETAXIINT_RCEN_MASK                                                                0x01000000L
#define SWRST_CONTROL_1__RESETPCFG_RCEN_MASK                                                                  0x02000000L
#define SWRST_CONTROL_1__RESETLNCT_RCEN_MASK                                                                  0x04000000L
#define SWRST_CONTROL_1__RESETMNTR_RCEN_MASK                                                                  0x08000000L
#define SWRST_CONTROL_1__RESETHLTR_RCEN_MASK                                                                  0x10000000L
#define SWRST_CONTROL_1__RESETCPM_RCEN_MASK                                                                   0x20000000L
#define SWRST_CONTROL_1__RESETPHY0_RCEN_MASK                                                                  0x40000000L
#define SWRST_CONTROL_1__STRAPVLD_RCEN_MASK                                                                   0x80000000L
//SWRST_CONTROL_2
#define SWRST_CONTROL_2__PORT0_COR_ATEN__SHIFT                                                                0x0
#define SWRST_CONTROL_2__PORT0_CFG_ATEN__SHIFT                                                                0x8
#define SWRST_CONTROL_2__PORT1_CFG_ATEN__SHIFT                                                                0x9
#define SWRST_CONTROL_2__PORT2_CFG_ATEN__SHIFT                                                                0xa
#define SWRST_CONTROL_2__PORT3_CFG_ATEN__SHIFT                                                                0xb
#define SWRST_CONTROL_2__PORT4_CFG_ATEN__SHIFT                                                                0xc
#define SWRST_CONTROL_2__PORT5_CFG_ATEN__SHIFT                                                                0xd
#define SWRST_CONTROL_2__PORT6_CFG_ATEN__SHIFT                                                                0xe
#define SWRST_CONTROL_2__PORT7_CFG_ATEN__SHIFT                                                                0xf
#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN__SHIFT                                                         0x18
#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN__SHIFT                                                          0x19
#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN__SHIFT                                                           0x1a
#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN__SHIFT                                                       0x1b
#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN__SHIFT                                                            0x1c
#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN__SHIFT                                                         0x1d
#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN__SHIFT                                                         0x1e
#define SWRST_CONTROL_2__PORT0_COR_ATEN_MASK                                                                  0x00000001L
#define SWRST_CONTROL_2__PORT0_CFG_ATEN_MASK                                                                  0x00000100L
#define SWRST_CONTROL_2__PORT1_CFG_ATEN_MASK                                                                  0x00000200L
#define SWRST_CONTROL_2__PORT2_CFG_ATEN_MASK                                                                  0x00000400L
#define SWRST_CONTROL_2__PORT3_CFG_ATEN_MASK                                                                  0x00000800L
#define SWRST_CONTROL_2__PORT4_CFG_ATEN_MASK                                                                  0x00001000L
#define SWRST_CONTROL_2__PORT5_CFG_ATEN_MASK                                                                  0x00002000L
#define SWRST_CONTROL_2__PORT6_CFG_ATEN_MASK                                                                  0x00004000L
#define SWRST_CONTROL_2__PORT7_CFG_ATEN_MASK                                                                  0x00008000L
#define SWRST_CONTROL_2__BIF0_GLOBAL_RESETATEN_MASK                                                           0x01000000L
#define SWRST_CONTROL_2__BIF0_CALIB_RESETATEN_MASK                                                            0x02000000L
#define SWRST_CONTROL_2__BIF0_CORE_RESETATEN_MASK                                                             0x04000000L
#define SWRST_CONTROL_2__BIF0_REGISTER_RESETATEN_MASK                                                         0x08000000L
#define SWRST_CONTROL_2__BIF0_PHY_RESETATEN_MASK                                                              0x10000000L
#define SWRST_CONTROL_2__BIF0_STICKY_RESETATEN_MASK                                                           0x20000000L
#define SWRST_CONTROL_2__BIF0_CONFIG_RESETATEN_MASK                                                           0x40000000L
//SWRST_CONTROL_3
#define SWRST_CONTROL_3__PCSRESET0_ATEN__SHIFT                                                                0x0
#define SWRST_CONTROL_3__PCSRESET1_ATEN__SHIFT                                                                0x1
#define SWRST_CONTROL_3__PCSRESET2_ATEN__SHIFT                                                                0x2
#define SWRST_CONTROL_3__PCSRESET3_ATEN__SHIFT                                                                0x3
#define SWRST_CONTROL_3__PCSRESET4_ATEN__SHIFT                                                                0x4
#define SWRST_CONTROL_3__PCSRESET5_ATEN__SHIFT                                                                0x5
#define SWRST_CONTROL_3__PCSRESET6_ATEN__SHIFT                                                                0x6
#define SWRST_CONTROL_3__PCSRESET7_ATEN__SHIFT                                                                0x7
#define SWRST_CONTROL_3__PCSRESET8_ATEN__SHIFT                                                                0x8
#define SWRST_CONTROL_3__PCSRESET9_ATEN__SHIFT                                                                0x9
#define SWRST_CONTROL_3__PCSRESET10_ATEN__SHIFT                                                               0xa
#define SWRST_CONTROL_3__PCSRESET11_ATEN__SHIFT                                                               0xb
#define SWRST_CONTROL_3__PCSRESET12_ATEN__SHIFT                                                               0xc
#define SWRST_CONTROL_3__PCSRESET13_ATEN__SHIFT                                                               0xd
#define SWRST_CONTROL_3__PCSRESET14_ATEN__SHIFT                                                               0xe
#define SWRST_CONTROL_3__PCSRESET15_ATEN__SHIFT                                                               0xf
#define SWRST_CONTROL_3__SWITCHCLK_ATEN__SHIFT                                                                0x15
#define SWRST_CONTROL_3__RESETAXIMST_ATEN__SHIFT                                                              0x16
#define SWRST_CONTROL_3__RESETAXISLV_ATEN__SHIFT                                                              0x17
#define SWRST_CONTROL_3__RESETAXIINT_ATEN__SHIFT                                                              0x18
#define SWRST_CONTROL_3__RESETPCFG_ATEN__SHIFT                                                                0x19
#define SWRST_CONTROL_3__RESETLNCT_ATEN__SHIFT                                                                0x1a
#define SWRST_CONTROL_3__RESETMNTR_ATEN__SHIFT                                                                0x1b
#define SWRST_CONTROL_3__RESETHLTR_ATEN__SHIFT                                                                0x1c
#define SWRST_CONTROL_3__RESETCPM_ATEN__SHIFT                                                                 0x1d
#define SWRST_CONTROL_3__RESETPHY0_ATEN__SHIFT                                                                0x1e
#define SWRST_CONTROL_3__STRAPVLD_ATEN__SHIFT                                                                 0x1f
#define SWRST_CONTROL_3__PCSRESET0_ATEN_MASK                                                                  0x00000001L
#define SWRST_CONTROL_3__PCSRESET1_ATEN_MASK                                                                  0x00000002L
#define SWRST_CONTROL_3__PCSRESET2_ATEN_MASK                                                                  0x00000004L
#define SWRST_CONTROL_3__PCSRESET3_ATEN_MASK                                                                  0x00000008L
#define SWRST_CONTROL_3__PCSRESET4_ATEN_MASK                                                                  0x00000010L
#define SWRST_CONTROL_3__PCSRESET5_ATEN_MASK                                                                  0x00000020L
#define SWRST_CONTROL_3__PCSRESET6_ATEN_MASK                                                                  0x00000040L
#define SWRST_CONTROL_3__PCSRESET7_ATEN_MASK                                                                  0x00000080L
#define SWRST_CONTROL_3__PCSRESET8_ATEN_MASK                                                                  0x00000100L
#define SWRST_CONTROL_3__PCSRESET9_ATEN_MASK                                                                  0x00000200L
#define SWRST_CONTROL_3__PCSRESET10_ATEN_MASK                                                                 0x00000400L
#define SWRST_CONTROL_3__PCSRESET11_ATEN_MASK                                                                 0x00000800L
#define SWRST_CONTROL_3__PCSRESET12_ATEN_MASK                                                                 0x00001000L
#define SWRST_CONTROL_3__PCSRESET13_ATEN_MASK                                                                 0x00002000L
#define SWRST_CONTROL_3__PCSRESET14_ATEN_MASK                                                                 0x00004000L
#define SWRST_CONTROL_3__PCSRESET15_ATEN_MASK                                                                 0x00008000L
#define SWRST_CONTROL_3__SWITCHCLK_ATEN_MASK                                                                  0x00200000L
#define SWRST_CONTROL_3__RESETAXIMST_ATEN_MASK                                                                0x00400000L
#define SWRST_CONTROL_3__RESETAXISLV_ATEN_MASK                                                                0x00800000L
#define SWRST_CONTROL_3__RESETAXIINT_ATEN_MASK                                                                0x01000000L
#define SWRST_CONTROL_3__RESETPCFG_ATEN_MASK                                                                  0x02000000L
#define SWRST_CONTROL_3__RESETLNCT_ATEN_MASK                                                                  0x04000000L
#define SWRST_CONTROL_3__RESETMNTR_ATEN_MASK                                                                  0x08000000L
#define SWRST_CONTROL_3__RESETHLTR_ATEN_MASK                                                                  0x10000000L
#define SWRST_CONTROL_3__RESETCPM_ATEN_MASK                                                                   0x20000000L
#define SWRST_CONTROL_3__RESETPHY0_ATEN_MASK                                                                  0x40000000L
#define SWRST_CONTROL_3__STRAPVLD_ATEN_MASK                                                                   0x80000000L
//SWRST_CONTROL_4
#define SWRST_CONTROL_4__PORT0_COR_WREN__SHIFT                                                                0x0
#define SWRST_CONTROL_4__PORT0_CFG_WREN__SHIFT                                                                0x8
#define SWRST_CONTROL_4__PORT1_CFG_WREN__SHIFT                                                                0x9
#define SWRST_CONTROL_4__PORT2_CFG_WREN__SHIFT                                                                0xa
#define SWRST_CONTROL_4__PORT3_CFG_WREN__SHIFT                                                                0xb
#define SWRST_CONTROL_4__PORT4_CFG_WREN__SHIFT                                                                0xc
#define SWRST_CONTROL_4__PORT5_CFG_WREN__SHIFT                                                                0xd
#define SWRST_CONTROL_4__PORT6_CFG_WREN__SHIFT                                                                0xe
#define SWRST_CONTROL_4__PORT7_CFG_WREN__SHIFT                                                                0xf
#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN__SHIFT                                                         0x18
#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN__SHIFT                                                          0x19
#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN__SHIFT                                                           0x1a
#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN__SHIFT                                                       0x1b
#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN__SHIFT                                                            0x1c
#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN__SHIFT                                                         0x1d
#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN__SHIFT                                                         0x1e
#define SWRST_CONTROL_4__PORT0_COR_WREN_MASK                                                                  0x00000001L
#define SWRST_CONTROL_4__PORT0_CFG_WREN_MASK                                                                  0x00000100L
#define SWRST_CONTROL_4__PORT1_CFG_WREN_MASK                                                                  0x00000200L
#define SWRST_CONTROL_4__PORT2_CFG_WREN_MASK                                                                  0x00000400L
#define SWRST_CONTROL_4__PORT3_CFG_WREN_MASK                                                                  0x00000800L
#define SWRST_CONTROL_4__PORT4_CFG_WREN_MASK                                                                  0x00001000L
#define SWRST_CONTROL_4__PORT5_CFG_WREN_MASK                                                                  0x00002000L
#define SWRST_CONTROL_4__PORT6_CFG_WREN_MASK                                                                  0x00004000L
#define SWRST_CONTROL_4__PORT7_CFG_WREN_MASK                                                                  0x00008000L
#define SWRST_CONTROL_4__BIF0_GLOBAL_WRRESETEN_MASK                                                           0x01000000L
#define SWRST_CONTROL_4__BIF0_CALIB_WRRESETEN_MASK                                                            0x02000000L
#define SWRST_CONTROL_4__BIF0_CORE_WRRESETEN_MASK                                                             0x04000000L
#define SWRST_CONTROL_4__BIF0_REGISTER_WRRESETEN_MASK                                                         0x08000000L
#define SWRST_CONTROL_4__BIF0_PHY_WRRESETEN_MASK                                                              0x10000000L
#define SWRST_CONTROL_4__BIF0_STICKY_WRRESETEN_MASK                                                           0x20000000L
#define SWRST_CONTROL_4__BIF0_CONFIG_WRRESETEN_MASK                                                           0x40000000L
//SWRST_CONTROL_5
#define SWRST_CONTROL_5__PCSRESET0_WREN__SHIFT                                                                0x0
#define SWRST_CONTROL_5__PCSRESET1_WREN__SHIFT                                                                0x1
#define SWRST_CONTROL_5__PCSRESET2_WREN__SHIFT                                                                0x2
#define SWRST_CONTROL_5__PCSRESET3_WREN__SHIFT                                                                0x3
#define SWRST_CONTROL_5__PCSRESET4_WREN__SHIFT                                                                0x4
#define SWRST_CONTROL_5__PCSRESET5_WREN__SHIFT                                                                0x5
#define SWRST_CONTROL_5__PCSRESET6_WREN__SHIFT                                                                0x6
#define SWRST_CONTROL_5__PCSRESET7_WREN__SHIFT                                                                0x7
#define SWRST_CONTROL_5__PCSRESET8_WREN__SHIFT                                                                0x8
#define SWRST_CONTROL_5__PCSRESET9_WREN__SHIFT                                                                0x9
#define SWRST_CONTROL_5__PCSRESET10_WREN__SHIFT                                                               0xa
#define SWRST_CONTROL_5__PCSRESET11_WREN__SHIFT                                                               0xb
#define SWRST_CONTROL_5__PCSRESET12_WREN__SHIFT                                                               0xc
#define SWRST_CONTROL_5__PCSRESET13_WREN__SHIFT                                                               0xd
#define SWRST_CONTROL_5__PCSRESET14_WREN__SHIFT                                                               0xe
#define SWRST_CONTROL_5__PCSRESET15_WREN__SHIFT                                                               0xf
#define SWRST_CONTROL_5__WRSWITCHCLK_EN__SHIFT                                                                0x15
#define SWRST_CONTROL_5__WRRESETAXIMST_EN__SHIFT                                                              0x16
#define SWRST_CONTROL_5__WRRESETAXISLV_EN__SHIFT                                                              0x17
#define SWRST_CONTROL_5__WRRESETAXIINT_EN__SHIFT                                                              0x18
#define SWRST_CONTROL_5__WRRESETPCFG_EN__SHIFT                                                                0x19
#define SWRST_CONTROL_5__WRRESETLNCT_EN__SHIFT                                                                0x1a
#define SWRST_CONTROL_5__WRRESETMNTR_EN__SHIFT                                                                0x1b
#define SWRST_CONTROL_5__WRRESETHLTR_EN__SHIFT                                                                0x1c
#define SWRST_CONTROL_5__WRRESETCPM_EN__SHIFT                                                                 0x1d
#define SWRST_CONTROL_5__WRRESETPHY0_EN__SHIFT                                                                0x1e
#define SWRST_CONTROL_5__WRSTRAPVLD_EN__SHIFT                                                                 0x1f
#define SWRST_CONTROL_5__PCSRESET0_WREN_MASK                                                                  0x00000001L
#define SWRST_CONTROL_5__PCSRESET1_WREN_MASK                                                                  0x00000002L
#define SWRST_CONTROL_5__PCSRESET2_WREN_MASK                                                                  0x00000004L
#define SWRST_CONTROL_5__PCSRESET3_WREN_MASK                                                                  0x00000008L
#define SWRST_CONTROL_5__PCSRESET4_WREN_MASK                                                                  0x00000010L
#define SWRST_CONTROL_5__PCSRESET5_WREN_MASK                                                                  0x00000020L
#define SWRST_CONTROL_5__PCSRESET6_WREN_MASK                                                                  0x00000040L
#define SWRST_CONTROL_5__PCSRESET7_WREN_MASK                                                                  0x00000080L
#define SWRST_CONTROL_5__PCSRESET8_WREN_MASK                                                                  0x00000100L
#define SWRST_CONTROL_5__PCSRESET9_WREN_MASK                                                                  0x00000200L
#define SWRST_CONTROL_5__PCSRESET10_WREN_MASK                                                                 0x00000400L
#define SWRST_CONTROL_5__PCSRESET11_WREN_MASK                                                                 0x00000800L
#define SWRST_CONTROL_5__PCSRESET12_WREN_MASK                                                                 0x00001000L
#define SWRST_CONTROL_5__PCSRESET13_WREN_MASK                                                                 0x00002000L
#define SWRST_CONTROL_5__PCSRESET14_WREN_MASK                                                                 0x00004000L
#define SWRST_CONTROL_5__PCSRESET15_WREN_MASK                                                                 0x00008000L
#define SWRST_CONTROL_5__WRSWITCHCLK_EN_MASK                                                                  0x00200000L
#define SWRST_CONTROL_5__WRRESETAXIMST_EN_MASK                                                                0x00400000L
#define SWRST_CONTROL_5__WRRESETAXISLV_EN_MASK                                                                0x00800000L
#define SWRST_CONTROL_5__WRRESETAXIINT_EN_MASK                                                                0x01000000L
#define SWRST_CONTROL_5__WRRESETPCFG_EN_MASK                                                                  0x02000000L
#define SWRST_CONTROL_5__WRRESETLNCT_EN_MASK                                                                  0x04000000L
#define SWRST_CONTROL_5__WRRESETMNTR_EN_MASK                                                                  0x08000000L
#define SWRST_CONTROL_5__WRRESETHLTR_EN_MASK                                                                  0x10000000L
#define SWRST_CONTROL_5__WRRESETCPM_EN_MASK                                                                   0x20000000L
#define SWRST_CONTROL_5__WRRESETPHY0_EN_MASK                                                                  0x40000000L
#define SWRST_CONTROL_5__WRSTRAPVLD_EN_MASK                                                                   0x80000000L
//SWRST_CONTROL_6
#define SWRST_CONTROL_6__HOLD_TRAINING_A__SHIFT                                                               0x0
#define SWRST_CONTROL_6__HOLD_TRAINING_B__SHIFT                                                               0x1
#define SWRST_CONTROL_6__HOLD_TRAINING_C__SHIFT                                                               0x2
#define SWRST_CONTROL_6__HOLD_TRAINING_D__SHIFT                                                               0x3
#define SWRST_CONTROL_6__HOLD_TRAINING_E__SHIFT                                                               0x4
#define SWRST_CONTROL_6__HOLD_TRAINING_F__SHIFT                                                               0x5
#define SWRST_CONTROL_6__HOLD_TRAINING_G__SHIFT                                                               0x6
#define SWRST_CONTROL_6__HOLD_TRAINING_H__SHIFT                                                               0x7
#define SWRST_CONTROL_6__HOLD_TRAINING_I__SHIFT                                                               0x8
#define SWRST_CONTROL_6__HOLD_TRAINING_J__SHIFT                                                               0x9
#define SWRST_CONTROL_6__HOLD_TRAINING_K__SHIFT                                                               0xa
#define SWRST_CONTROL_6__HOLD_TRAINING_A_MASK                                                                 0x00000001L
#define SWRST_CONTROL_6__HOLD_TRAINING_B_MASK                                                                 0x00000002L
#define SWRST_CONTROL_6__HOLD_TRAINING_C_MASK                                                                 0x00000004L
#define SWRST_CONTROL_6__HOLD_TRAINING_D_MASK                                                                 0x00000008L
#define SWRST_CONTROL_6__HOLD_TRAINING_E_MASK                                                                 0x00000010L
#define SWRST_CONTROL_6__HOLD_TRAINING_F_MASK                                                                 0x00000020L
#define SWRST_CONTROL_6__HOLD_TRAINING_G_MASK                                                                 0x00000040L
#define SWRST_CONTROL_6__HOLD_TRAINING_H_MASK                                                                 0x00000080L
#define SWRST_CONTROL_6__HOLD_TRAINING_I_MASK                                                                 0x00000100L
#define SWRST_CONTROL_6__HOLD_TRAINING_J_MASK                                                                 0x00000200L
#define SWRST_CONTROL_6__HOLD_TRAINING_K_MASK                                                                 0x00000400L
//SWRST_EP_COMMAND_0
#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY__SHIFT                                                          0x0
#define SWRST_EP_COMMAND_0__EP_HOT_RESET__SHIFT                                                               0x8
#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET__SHIFT                                                            0x9
#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET__SHIFT                                                            0xa
#define SWRST_EP_COMMAND_0__EP_CFG_RESET_ONLY_MASK                                                            0x00000001L
#define SWRST_EP_COMMAND_0__EP_HOT_RESET_MASK                                                                 0x00000100L
#define SWRST_EP_COMMAND_0__EP_LNKDWN_RESET_MASK                                                              0x00000200L
#define SWRST_EP_COMMAND_0__EP_LNKDIS_RESET_MASK                                                              0x00000400L
//SWRST_EP_CONTROL_0
#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN__SHIFT                                                       0x0
#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN__SHIFT                                                            0x8
#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN__SHIFT                                                         0x9
#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN__SHIFT                                                         0xa
#define SWRST_EP_CONTROL_0__EP_CFG_RESET_ONLY_EN_MASK                                                         0x00000001L
#define SWRST_EP_CONTROL_0__EP_HOT_RESET_EN_MASK                                                              0x00000100L
#define SWRST_EP_CONTROL_0__EP_LNKDWN_RESET_EN_MASK                                                           0x00000200L
#define SWRST_EP_CONTROL_0__EP_LNKDIS_RESET_EN_MASK                                                           0x00000400L
//CPM_CONTROL
#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE__SHIFT                                                              0x0
#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE__SHIFT                                                             0x1
#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE__SHIFT                                                            0x2
#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE__SHIFT                                                            0x5
#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE__SHIFT                                                            0x6
#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE__SHIFT                                                            0x7
#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE__SHIFT                                                           0x8
#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY__SHIFT                                                             0x9
#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY__SHIFT                                                            0xa
#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY__SHIFT                                                           0xb
#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY__SHIFT                                                           0xc
#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY__SHIFT                                                          0xd
#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE__SHIFT                                                              0xe
#define CPM_CONTROL__RCVR_DET_CLK_ENABLE__SHIFT                                                               0xf
#define CPM_CONTROL__FAST_TXCLK_LATENCY__SHIFT                                                                0x11
#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE__SHIFT                                                              0x16
#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY__SHIFT                                                             0x17
#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE__SHIFT                                                       0x18
#define CPM_CONTROL__SPARE_REGS__SHIFT                                                                        0x19
#define CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK                                                                0x00000001L
#define CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK                                                               0x00000002L
#define CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK                                                              0x00000004L
#define CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK                                                              0x00000020L
#define CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK                                                              0x00000040L
#define CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK                                                              0x00000080L
#define CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK                                                             0x00000100L
#define CPM_CONTROL__LCLK_DYN_GATE_LATENCY_MASK                                                               0x00000200L
#define CPM_CONTROL__TXCLK_DYN_GATE_LATENCY_MASK                                                              0x00000400L
#define CPM_CONTROL__TXCLK_PERM_GATE_LATENCY_MASK                                                             0x00000800L
#define CPM_CONTROL__TXCLK_REGS_GATE_LATENCY_MASK                                                             0x00001000L
#define CPM_CONTROL__REFCLK_REGS_GATE_LATENCY_MASK                                                            0x00002000L
#define CPM_CONTROL__LCLK_GATE_TXCLK_FREE_MASK                                                                0x00004000L
#define CPM_CONTROL__RCVR_DET_CLK_ENABLE_MASK                                                                 0x00008000L
#define CPM_CONTROL__FAST_TXCLK_LATENCY_MASK                                                                  0x000E0000L
#define CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK                                                                0x00400000L
#define CPM_CONTROL__REFCLK_XSTCLK_LATENCY_MASK                                                               0x00800000L
#define CPM_CONTROL__CLKREQb_UNGATE_TXCLK_ENABLE_MASK                                                         0x01000000L
#define CPM_CONTROL__SPARE_REGS_MASK                                                                          0xFE000000L
//SMN_APERTURE_ID_A
#define SMN_APERTURE_ID_A__SMU_APERTURE_ID__SHIFT                                                             0x0
#define SMN_APERTURE_ID_A__PCS_APERTURE_ID__SHIFT                                                             0xc
#define SMN_APERTURE_ID_A__SMU_APERTURE_ID_MASK                                                               0x00000FFFL
#define SMN_APERTURE_ID_A__PCS_APERTURE_ID_MASK                                                               0x00FFF000L
//SMN_APERTURE_ID_B
#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID__SHIFT                                                           0x0
#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID__SHIFT                                                            0xc
#define SMN_APERTURE_ID_B__IOHUB_APERTURE_ID_MASK                                                             0x00000FFFL
#define SMN_APERTURE_ID_B__NBIF_APERTURE_ID_MASK                                                              0x00FFF000L
//RSMU_MASTER_CONTROL
#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE__SHIFT                                           0x0
#define RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE_MASK                                             0x00000001L
//RSMU_SLAVE_CONTROL
#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO__SHIFT                                        0x0
#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE__SHIFT                                     0x2
#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO_MASK                                          0x00000001L
#define RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE_MASK                                       0x00000004L
//RSMU_POWER_GATING_CONTROL
#define RSMU_POWER_GATING_CONTROL__CFG_PG_HYSTERESIS__SHIFT                                                   0x0
#define RSMU_POWER_GATING_CONTROL__CFG_PG_EN__SHIFT                                                           0x8
#define RSMU_POWER_GATING_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT                                                 0x9
#define RSMU_POWER_GATING_CONTROL__CFG_PG_HYSTERESIS_MASK                                                     0x000000FFL
#define RSMU_POWER_GATING_CONTROL__CFG_PG_EN_MASK                                                             0x00000100L
#define RSMU_POWER_GATING_CONTROL__CFG_IDLE_HYSTERESIS_MASK                                                   0x00003E00L
//RSMU_BIOS_TIMER_CMD
#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS__SHIFT                                                      0x0
#define RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS_MASK                                                        0xFFFFFFFFL
//RSMU_BIOS_TIMER_CNTL
#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE__SHIFT                                                        0x0
#define RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE_MASK                                                          0x000000FFL
//LNCNT_CONTROL
#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN__SHIFT                                                               0x0
#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN__SHIFT                                                               0x1
#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN__SHIFT                                                              0x2
#define LNCNT_CONTROL__CFG_LNC_OVRD_EN__SHIFT                                                                 0x3
#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL__SHIFT                                                                0x4
#define LNCNT_CONTROL__CFG_LNC_WINDOW_EN_MASK                                                                 0x00000001L
#define LNCNT_CONTROL__CFG_LNC_BW_CNT_EN_MASK                                                                 0x00000002L
#define LNCNT_CONTROL__CFG_LNC_CMN_CNT_EN_MASK                                                                0x00000004L
#define LNCNT_CONTROL__CFG_LNC_OVRD_EN_MASK                                                                   0x00000008L
#define LNCNT_CONTROL__CFG_LNC_OVRD_VAL_MASK                                                                  0x00000010L
//CFG_LNC_WINDOW_REGISTER
#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW__SHIFT                                                        0x0
#define CFG_LNC_WINDOW_REGISTER__CFG_LNC_WINDOW_MASK                                                          0x00FFFFFFL
//LNCNT_QUAN_THRD
#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD__SHIFT                                                          0x0
#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD__SHIFT                                                         0x4
#define LNCNT_QUAN_THRD__CFG_LNC_BW_QUAN_THRD_MASK                                                            0x00000007L
#define LNCNT_QUAN_THRD__CFG_LNC_CMN_QUAN_THRD_MASK                                                           0x00000070L
//LNCNT_WEIGHT
#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT__SHIFT                                                                0x0
#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT__SHIFT                                                               0x10
#define LNCNT_WEIGHT__CFG_LNC_BW_WEIGHT_MASK                                                                  0x0000FFFFL
#define LNCNT_WEIGHT__CFG_LNC_CMN_WEIGHT_MASK                                                                 0xFFFF0000L
//LNC_TOTAL_WACC_REGISTER
#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC__SHIFT                                                        0x0
#define LNC_TOTAL_WACC_REGISTER__LNC_TOTAL_WACC_MASK                                                          0xFFFFFFFFL
//LNC_BW_WACC_REGISTER
#define LNC_BW_WACC_REGISTER__LNC_BW_WACC__SHIFT                                                              0x0
#define LNC_BW_WACC_REGISTER__LNC_BW_WACC_MASK                                                                0xFFFFFFFFL
//LNC_CMN_WACC_REGISTER
#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC__SHIFT                                                            0x0
#define LNC_CMN_WACC_REGISTER__LNC_CMN_WACC_MASK                                                              0xFFFFFFFFL
//SMU_INT_PIN_SHARING_PORT_INDICATOR
#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS__SHIFT                                 0x0
#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS__SHIFT                                             0x8
#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS__SHIFT                                             0x10
#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LINK_MANAGEMENT_INT_STATUS_MASK                                   0x000000FFL
#define SMU_INT_PIN_SHARING_PORT_INDICATOR__LTR_INT_STATUS_MASK                                               0x0000FF00L
#define SMU_INT_PIN_SHARING_PORT_INDICATOR__DPC_INT_STATUS_MASK                                               0x00FF0000L
//SMU_PCIE_FENCED1_REG
#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN__SHIFT                                           0x0
#define SMU_PCIE_FENCED1_REG__MP0_PCIE_CROSSFIRE_LOCKDOWN_EN_MASK                                             0x00000001L
//SMU_PCIE_FENCED2_REG


// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns0_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                   0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                         0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                        0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                        0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                      0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                     0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                      0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                 0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                            0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__BG_EN__SHIFT                                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                              0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK                                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK                                            0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK                                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK                                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN__BG_EN_MASK                                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                      0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                              0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                  0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                 0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                               0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                             0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK                                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                         0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                      0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                             0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK                                          0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__bypass_bg__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__vref_sel_fastreg__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__chop_en__SHIFT                                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__NC74__SHIFT                                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__RESERVED_15_8__SHIFT                                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__bypass_bg_MASK                                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__vref_sel_fastreg_MASK                                            0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__chop_en_MASK                                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__NC74_MASK                                                        0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG__RESERVED_15_8_MASK                                               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                    0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__STAT_MASK                                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                           0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                      0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                    0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                 0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                          0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                  0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                        0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                       0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                       0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                     0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                     0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                  0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__BG_EN__SHIFT                                               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                             0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK                                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK                                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK                                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK                                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN__BG_EN_MASK                                                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                     0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                     0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                       0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                 0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK                                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                        0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                     0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                            0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK                                         0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__bypass_bg__SHIFT                                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__vref_sel_fastreg__SHIFT                                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__chop_en__SHIFT                                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__NC74__SHIFT                                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__RESERVED_15_8__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__bypass_bg_MASK                                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__vref_sel_fastreg_MASK                                           0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__chop_en_MASK                                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__NC74_MASK                                                       0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG__RESERVED_15_8_MASK                                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__STAT_MASK                                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                          0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                     0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                         0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                   0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK                                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL


// addressBlock: nbio_pipe_pcs_lcu_pcie_pcs_prime_phyx4_pcs_prime_dir
//DXIO_HWDID
#define DXIO_HWDID__Hardware_Revision__SHIFT                                                                  0x0
#define DXIO_HWDID__Hardware_Minor_Version_Number__SHIFT                                                      0x6
#define DXIO_HWDID__Hardware_Major_Version_Number__SHIFT                                                      0xd
#define DXIO_HWDID__Protocol_PCS__SHIFT                                                                       0x14
#define DXIO_HWDID__PCS_Vendor_ID__SHIFT                                                                      0x1a
#define DXIO_HWDID__Hardware_Revision_MASK                                                                    0x0000003FL
#define DXIO_HWDID__Hardware_Minor_Version_Number_MASK                                                        0x00001FC0L
#define DXIO_HWDID__Hardware_Major_Version_Number_MASK                                                        0x000FE000L
#define DXIO_HWDID__Protocol_PCS_MASK                                                                         0x03F00000L
#define DXIO_HWDID__PCS_Vendor_ID_MASK                                                                        0xFC000000L
//DXIO_LINKAGE_LANEGRP
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses__SHIFT                                             0x0
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size__SHIFT                                                 0x2
#define DXIO_LINKAGE_LANEGRP__Index_Offset__SHIFT                                                             0x6
#define DXIO_LINKAGE_LANEGRP__Presence__SHIFT                                                                 0x14
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Indirect_Accesses_MASK                                               0x00000001L
#define DXIO_LINKAGE_LANEGRP__Lane_Group_Aperture_Size_MASK                                                   0x0000003CL
#define DXIO_LINKAGE_LANEGRP__Index_Offset_MASK                                                               0x000FFFC0L
#define DXIO_LINKAGE_LANEGRP__Presence_MASK                                                                   0x0FF00000L
//DXIO_LINKAGE_KPDMX
#define DXIO_LINKAGE_KPDMX__Overlay__SHIFT                                                                    0x1
#define DXIO_LINKAGE_KPDMX__Base_Offset__SHIFT                                                                0x6
#define DXIO_LINKAGE_KPDMX__Presence__SHIFT                                                                   0x14
#define DXIO_LINKAGE_KPDMX__Overlay_MASK                                                                      0x00000002L
#define DXIO_LINKAGE_KPDMX__Base_Offset_MASK                                                                  0x000FFFC0L
#define DXIO_LINKAGE_KPDMX__Presence_MASK                                                                     0x0FF00000L
//DXIO_LINKAGE_KPMX
#define DXIO_LINKAGE_KPMX__Overlay__SHIFT                                                                     0x1
#define DXIO_LINKAGE_KPMX__Frame_Size__SHIFT                                                                  0x2
#define DXIO_LINKAGE_KPMX__Base_Offset__SHIFT                                                                 0x6
#define DXIO_LINKAGE_KPMX__Overlay_MASK                                                                       0x00000002L
#define DXIO_LINKAGE_KPMX__Frame_Size_MASK                                                                    0x0000003CL
#define DXIO_LINKAGE_KPMX__Base_Offset_MASK                                                                   0x000FFFC0L
//DXIO_LINKAGE_KPFIFO
#define DXIO_LINKAGE_KPFIFO__Overlay__SHIFT                                                                   0x1
#define DXIO_LINKAGE_KPFIFO__Frame_Size__SHIFT                                                                0x2
#define DXIO_LINKAGE_KPFIFO__Base_Offset__SHIFT                                                               0x6
#define DXIO_LINKAGE_KPFIFO__Overlay_MASK                                                                     0x00000002L
#define DXIO_LINKAGE_KPFIFO__Frame_Size_MASK                                                                  0x0000003CL
#define DXIO_LINKAGE_KPFIFO__Base_Offset_MASK                                                                 0x000FFFC0L
//DXIO_LINKAGE_KPNP
#define DXIO_LINKAGE_KPNP__Overlay__SHIFT                                                                     0x1
#define DXIO_LINKAGE_KPNP__Frame_Size__SHIFT                                                                  0x2
#define DXIO_LINKAGE_KPNP__Base_Offset__SHIFT                                                                 0x6
#define DXIO_LINKAGE_KPNP__Overlay_MASK                                                                       0x00000002L
#define DXIO_LINKAGE_KPNP__Frame_Size_MASK                                                                    0x0000003CL
#define DXIO_LINKAGE_KPNP__Base_Offset_MASK                                                                   0x000FFFC0L
//PCS_LANEGRP0_MAPPING
#define PCS_LANEGRP0_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP0_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP0_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP0_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP0_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP0_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP1_MAPPING
#define PCS_LANEGRP1_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP1_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP1_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP1_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP1_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP1_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP2_MAPPING
#define PCS_LANEGRP2_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP2_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP2_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP2_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP2_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP2_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP3_MAPPING
#define PCS_LANEGRP3_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP3_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP3_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP3_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP3_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP3_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP4_MAPPING
#define PCS_LANEGRP4_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP4_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP4_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP4_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP4_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP4_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP5_MAPPING
#define PCS_LANEGRP5_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP5_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP5_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP5_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP5_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP5_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP6_MAPPING
#define PCS_LANEGRP6_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP6_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP6_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP6_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP6_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP6_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//PCS_LANEGRP7_MAPPING
#define PCS_LANEGRP7_MAPPING__Lane_Shift__SHIFT                                                               0x0
#define PCS_LANEGRP7_MAPPING__Target_Mux_Position__SHIFT                                                      0x5
#define PCS_LANEGRP7_MAPPING__Lane_Connections__SHIFT                                                         0x10
#define PCS_LANEGRP7_MAPPING__Lane_Shift_MASK                                                                 0x0000001FL
#define PCS_LANEGRP7_MAPPING__Target_Mux_Position_MASK                                                        0x000001E0L
#define PCS_LANEGRP7_MAPPING__Lane_Connections_MASK                                                           0xFFFF0000L
//MAC_CAPABILITIES1
#define MAC_CAPABILITIES1__Number_of_Lanes__SHIFT                                                             0x0
#define MAC_CAPABILITIES1__Number_of_Engines__SHIFT                                                           0x8
#define MAC_CAPABILITIES1__Number_of_Lanes_MASK                                                               0x0000003FL
#define MAC_CAPABILITIES1__Number_of_Engines_MASK                                                             0x00003F00L
//MAC_CAPABILITIES2
#define MAC_CAPABILITIES2__reserved__SHIFT                                                                    0x0
#define MAC_CAPABILITIES2__reserved_MASK                                                                      0x00000001L
//PCS_CAPABILITIES
#define PCS_CAPABILITIES__Number_of_Lanes__SHIFT                                                              0x0
#define PCS_CAPABILITIES__Number_of_Lanes_MASK                                                                0x0000003FL
//PCS_EXTENDED_CAP
#define PCS_EXTENDED_CAP__Next_Capability_Pointer__SHIFT                                                      0x2
#define PCS_EXTENDED_CAP__Next_Capability_Pointer_MASK                                                        0x000FFFFCL
//PCS_APERTURE0_LOC
#define PCS_APERTURE0_LOC__PCS_Indirect__SHIFT                                                                0x0
#define PCS_APERTURE0_LOC__Overlay__SHIFT                                                                     0x1
#define PCS_APERTURE0_LOC__PCS_Aperture_Size__SHIFT                                                           0x2
#define PCS_APERTURE0_LOC__Aperture_Offset__SHIFT                                                             0x6
#define PCS_APERTURE0_LOC__PCS_Indirect_MASK                                                                  0x00000001L
#define PCS_APERTURE0_LOC__Overlay_MASK                                                                       0x00000002L
#define PCS_APERTURE0_LOC__PCS_Aperture_Size_MASK                                                             0x0000003CL
#define PCS_APERTURE0_LOC__Aperture_Offset_MASK                                                               0x000FFFC0L
//PCS_APERTURE0_IDX
#define PCS_APERTURE0_IDX__PCS_Index__SHIFT                                                                   0x6
#define PCS_APERTURE0_IDX__PCS_Index_MASK                                                                     0xFFFFFFC0L
//PCS_APERTURE1_LOC
#define PCS_APERTURE1_LOC__PCS_Indirect__SHIFT                                                                0x0
#define PCS_APERTURE1_LOC__Overlay__SHIFT                                                                     0x1
#define PCS_APERTURE1_LOC__PCS_Aperture_Size__SHIFT                                                           0x2
#define PCS_APERTURE1_LOC__Aperture_Offset__SHIFT                                                             0x6
#define PCS_APERTURE1_LOC__PCS_Indirect_MASK                                                                  0x00000001L
#define PCS_APERTURE1_LOC__Overlay_MASK                                                                       0x00000002L
#define PCS_APERTURE1_LOC__PCS_Aperture_Size_MASK                                                             0x0000003CL
#define PCS_APERTURE1_LOC__Aperture_Offset_MASK                                                               0x000FFFC0L
//PCS_APERTURE1_IDX
#define PCS_APERTURE1_IDX__PCS_Index__SHIFT                                                                   0x6
#define PCS_APERTURE1_IDX__PCS_Index_MASK                                                                     0xFFFFFFC0L
//PCS_APERTURE2_LOC
#define PCS_APERTURE2_LOC__PCS_Indirect__SHIFT                                                                0x0
#define PCS_APERTURE2_LOC__Overlay__SHIFT                                                                     0x1
#define PCS_APERTURE2_LOC__PCS_Aperture_Size__SHIFT                                                           0x2
#define PCS_APERTURE2_LOC__Aperture_Offset__SHIFT                                                             0x6
#define PCS_APERTURE2_LOC__PCS_Indirect_MASK                                                                  0x00000001L
#define PCS_APERTURE2_LOC__Overlay_MASK                                                                       0x00000002L
#define PCS_APERTURE2_LOC__PCS_Aperture_Size_MASK                                                             0x0000003CL
#define PCS_APERTURE2_LOC__Aperture_Offset_MASK                                                               0x000FFFC0L
//PCS_APERTURE2_IDX
#define PCS_APERTURE2_IDX__PCS_Index__SHIFT                                                                   0x6
#define PCS_APERTURE2_IDX__PCS_Index_MASK                                                                     0xFFFFFFC0L
//PCS_APERTURE3_LOC
#define PCS_APERTURE3_LOC__PCS_Indirect__SHIFT                                                                0x0
#define PCS_APERTURE3_LOC__Overlay__SHIFT                                                                     0x1
#define PCS_APERTURE3_LOC__PCS_Aperture_Size__SHIFT                                                           0x2
#define PCS_APERTURE3_LOC__Aperture_Offset__SHIFT                                                             0x6
#define PCS_APERTURE3_LOC__PCS_Indirect_MASK                                                                  0x00000001L
#define PCS_APERTURE3_LOC__Overlay_MASK                                                                       0x00000002L
#define PCS_APERTURE3_LOC__PCS_Aperture_Size_MASK                                                             0x0000003CL
#define PCS_APERTURE3_LOC__Aperture_Offset_MASK                                                               0x000FFFC0L
//PCS_APERTURE3_IDX
#define PCS_APERTURE3_IDX__PCS_Index__SHIFT                                                                   0x6
#define PCS_APERTURE3_IDX__PCS_Index_MASK                                                                     0xFFFFFFC0L
//DXIO_CFG_SOFT_RESET
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset0__SHIFT                                                       0x0
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset1__SHIFT                                                       0x1
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset2__SHIFT                                                       0x2
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset3__SHIFT                                                       0x3
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset4__SHIFT                                                       0x4
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset5__SHIFT                                                       0x5
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset6__SHIFT                                                       0x6
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset7__SHIFT                                                       0x7
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset0_MASK                                                         0x00000001L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset1_MASK                                                         0x00000002L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset2_MASK                                                         0x00000004L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset3_MASK                                                         0x00000008L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset4_MASK                                                         0x00000010L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset5_MASK                                                         0x00000020L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset6_MASK                                                         0x00000040L
#define DXIO_CFG_SOFT_RESET__shadow_debug_reset7_MASK                                                         0x00000080L
//KPX_LANE_DATA_SOFT_RESET1
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset32__SHIFT                                     0x0
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset33__SHIFT                                     0x1
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset34__SHIFT                                     0x2
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset35__SHIFT                                     0x3
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset36__SHIFT                                     0x4
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset37__SHIFT                                     0x5
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset32_MASK                                       0x00000001L
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset33_MASK                                       0x00000002L
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset34_MASK                                       0x00000004L
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset35_MASK                                       0x00000008L
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset36_MASK                                       0x00000010L
#define KPX_LANE_DATA_SOFT_RESET1__PCS_PHY_per_lane_serdes_reset37_MASK                                       0x00000020L
//KPX_LANE_DATA_SOFT_RESET
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset0__SHIFT                                       0x0
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset1__SHIFT                                       0x1
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset2__SHIFT                                       0x2
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset3__SHIFT                                       0x3
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset4__SHIFT                                       0x4
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset5__SHIFT                                       0x5
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset6__SHIFT                                       0x6
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset7__SHIFT                                       0x7
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset8__SHIFT                                       0x8
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset9__SHIFT                                       0x9
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset10__SHIFT                                      0xa
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset11__SHIFT                                      0xb
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset12__SHIFT                                      0xc
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset13__SHIFT                                      0xd
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset14__SHIFT                                      0xe
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset15__SHIFT                                      0xf
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset16__SHIFT                                      0x10
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset17__SHIFT                                      0x11
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset18__SHIFT                                      0x12
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset19__SHIFT                                      0x13
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset20__SHIFT                                      0x14
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset21__SHIFT                                      0x15
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset22__SHIFT                                      0x16
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset23__SHIFT                                      0x17
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset24__SHIFT                                      0x18
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset25__SHIFT                                      0x19
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset26__SHIFT                                      0x1a
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset27__SHIFT                                      0x1b
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset28__SHIFT                                      0x1c
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset29__SHIFT                                      0x1d
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset30__SHIFT                                      0x1e
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset31__SHIFT                                      0x1f
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset0_MASK                                         0x00000001L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset1_MASK                                         0x00000002L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset2_MASK                                         0x00000004L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset3_MASK                                         0x00000008L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset4_MASK                                         0x00000010L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset5_MASK                                         0x00000020L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset6_MASK                                         0x00000040L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset7_MASK                                         0x00000080L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset8_MASK                                         0x00000100L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset9_MASK                                         0x00000200L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset10_MASK                                        0x00000400L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset11_MASK                                        0x00000800L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset12_MASK                                        0x00001000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset13_MASK                                        0x00002000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset14_MASK                                        0x00004000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset15_MASK                                        0x00008000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset16_MASK                                        0x00010000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset17_MASK                                        0x00020000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset18_MASK                                        0x00040000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset19_MASK                                        0x00080000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset20_MASK                                        0x00100000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset21_MASK                                        0x00200000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset22_MASK                                        0x00400000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset23_MASK                                        0x00800000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset24_MASK                                        0x01000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset25_MASK                                        0x02000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset26_MASK                                        0x04000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset27_MASK                                        0x08000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset28_MASK                                        0x10000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset29_MASK                                        0x20000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset30_MASK                                        0x40000000L
#define KPX_LANE_DATA_SOFT_RESET__PCS_PHY_per_lane_serdes_reset31_MASK                                        0x80000000L
//KPX_PMA_INFO_SOFT_RESET
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset0__SHIFT                                         0x10
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset1__SHIFT                                         0x11
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset2__SHIFT                                         0x12
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset3__SHIFT                                         0x13
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset4__SHIFT                                         0x14
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset5__SHIFT                                         0x15
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset6__SHIFT                                         0x16
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset7__SHIFT                                         0x17
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset0_MASK                                           0x00010000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset1_MASK                                           0x00020000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset2_MASK                                           0x00040000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset3_MASK                                           0x00080000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset4_MASK                                           0x00100000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset5_MASK                                           0x00200000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset6_MASK                                           0x00400000L
#define KPX_PMA_INFO_SOFT_RESET__PCS_PHY_per_PMA_serdes_reset7_MASK                                           0x00800000L
//PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy0__SHIFT                                     0x0
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy1__SHIFT                                     0x1
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy2__SHIFT                                     0x2
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy3__SHIFT                                     0x3
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy4__SHIFT                                     0x4
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy5__SHIFT                                     0x5
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy6__SHIFT                                     0x6
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy7__SHIFT                                     0x7
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy0_MASK                                       0x00000001L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy1_MASK                                       0x00000002L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy2_MASK                                       0x00000004L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy3_MASK                                       0x00000008L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy4_MASK                                       0x00000010L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy5_MASK                                       0x00000020L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy6_MASK                                       0x00000040L
#define PCS_PRIME_PHYX4_PCS_PMA_SOFT_RESET__PCS_PHY_soft_ResetPhy7_MASK                                       0x00000080L
//PCS_SOFT_RESET
#define PCS_SOFT_RESET__PCS_Soft_Reset__SHIFT                                                                 0x0
#define PCS_SOFT_RESET__PCS_Soft_Reset_MASK                                                                   0x00000001L
//PCS_LCU_CNTL
#define PCS_LCU_CNTL__PCS_LCU_PERM_CLKGATE_EN__SHIFT                                                          0x0
#define PCS_LCU_CNTL__PCS_LCU_POWER_GATING__SHIFT                                                             0x1
#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_EN__SHIFT                                                           0x7
#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_TIMER__SHIFT                                                        0x8
#define PCS_LCU_CNTL__SMU_INITIATOR_ID__SHIFT                                                                 0x10
#define PCS_LCU_CNTL__SMU_UNIT_ID__SHIFT                                                                      0x18
#define PCS_LCU_CNTL__PCS_LCU_PERM_CLKGATE_EN_MASK                                                            0x00000001L
#define PCS_LCU_CNTL__PCS_LCU_POWER_GATING_MASK                                                               0x00000002L
#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_EN_MASK                                                             0x00000080L
#define PCS_LCU_CNTL__PCS_LCU_DYNAMIC_CLK_TIMER_MASK                                                          0x0000FF00L
#define PCS_LCU_CNTL__SMU_INITIATOR_ID_MASK                                                                   0x00FF0000L
#define PCS_LCU_CNTL__SMU_UNIT_ID_MASK                                                                        0x3F000000L
//PCS_PIPE_PER_LANE_SOFT_RESET
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane0_soft_reset__SHIFT                                            0x0
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane1_soft_reset__SHIFT                                            0x1
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane2_soft_reset__SHIFT                                            0x2
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane3_soft_reset__SHIFT                                            0x3
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane4_soft_reset__SHIFT                                            0x4
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane5_soft_reset__SHIFT                                            0x5
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane6_soft_reset__SHIFT                                            0x6
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane7_soft_reset__SHIFT                                            0x7
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane8_soft_reset__SHIFT                                            0x8
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane9_soft_reset__SHIFT                                            0x9
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane10_soft_reset__SHIFT                                           0xa
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane11_soft_reset__SHIFT                                           0xb
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane12_soft_reset__SHIFT                                           0xc
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane13_soft_reset__SHIFT                                           0xd
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane14_soft_reset__SHIFT                                           0xe
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane15_soft_reset__SHIFT                                           0xf
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane0_soft_reset_MASK                                              0x00000001L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane1_soft_reset_MASK                                              0x00000002L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane2_soft_reset_MASK                                              0x00000004L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane3_soft_reset_MASK                                              0x00000008L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane4_soft_reset_MASK                                              0x00000010L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane5_soft_reset_MASK                                              0x00000020L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane6_soft_reset_MASK                                              0x00000040L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane7_soft_reset_MASK                                              0x00000080L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane8_soft_reset_MASK                                              0x00000100L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane9_soft_reset_MASK                                              0x00000200L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane10_soft_reset_MASK                                             0x00000400L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane11_soft_reset_MASK                                             0x00000800L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane12_soft_reset_MASK                                             0x00001000L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane13_soft_reset_MASK                                             0x00002000L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane14_soft_reset_MASK                                             0x00004000L
#define PCS_PIPE_PER_LANE_SOFT_RESET__pipe_lane15_soft_reset_MASK                                             0x00008000L


// addressBlock: nbio_lcu_kpfifo_kpfifo0_kpfifo_dir
//KPFIFO0_PRI_TX_FIFO_HSCID
#define KPFIFO0_PRI_TX_FIFO_HSCID__HwRev__SHIFT                                                               0x0
#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT                                                            0x6
#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT                                                            0xd
#define KPFIFO0_PRI_TX_FIFO_HSCID__HwRev_MASK                                                                 0x0000003FL
#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMinVer_MASK                                                              0x00001FC0L
#define KPFIFO0_PRI_TX_FIFO_HSCID__HwMajVer_MASK                                                              0x000FE000L
//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT                                                     0x0
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT                                                  0x10
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT                                                 0x1a
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK                                                       0x000000FFL
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK                                                   0x04000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK                                                     0x80000000L
//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT                                                     0x0
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT                                                  0x10
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT                                                 0x1a
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK                                                       0x000000FFL
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK                                                   0x04000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK                                                     0x80000000L
//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT                                                     0x0
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT                                                  0x10
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT                                                 0x1a
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK                                                       0x000000FFL
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK                                                   0x04000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK                                                     0x80000000L
//KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT                                                     0x0
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT                                                  0x10
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT                                                 0x1a
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK                                                       0x000000FFL
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK                                                   0x04000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO0_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK                                                     0x80000000L
//KPFIFO0_PCS_PMA_SOFT_RESET
#define KPFIFO0_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT                                           0x0
#define KPFIFO0_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK                                             0x00000001L


// addressBlock: nbio_lcu_kpnp_kpnp0_kpnp_dir
//KPNP_SNPS0_KPNP_HWSCVER
#define KPNP_SNPS0_KPNP_HWSCVER__hw_revision__SHIFT                                                           0x0
#define KPNP_SNPS0_KPNP_HWSCVER__hw_minor_version_number__SHIFT                                               0x6
#define KPNP_SNPS0_KPNP_HWSCVER__hw_major_version_number__SHIFT                                               0xd
#define KPNP_SNPS0_KPNP_HWSCVER__hw_revision_MASK                                                             0x0000003FL
#define KPNP_SNPS0_KPNP_HWSCVER__hw_minor_version_number_MASK                                                 0x00001FC0L
#define KPNP_SNPS0_KPNP_HWSCVER__hw_major_version_number_MASK                                                 0x000FE000L
//KPNP_SNPS0_KPNP_PHY_INFO
#define KPNP_SNPS0_KPNP_PHY_INFO__HwRev__SHIFT                                                                0x0
#define KPNP_SNPS0_KPNP_PHY_INFO__PHYVer__SHIFT                                                               0x6
#define KPNP_SNPS0_KPNP_PHY_INFO__Technology__SHIFT                                                           0xd
#define KPNP_SNPS0_KPNP_PHY_INFO__Type__SHIFT                                                                 0x14
#define KPNP_SNPS0_KPNP_PHY_INFO__VendorID__SHIFT                                                             0x1a
#define KPNP_SNPS0_KPNP_PHY_INFO__HwRev_MASK                                                                  0x0000003FL
#define KPNP_SNPS0_KPNP_PHY_INFO__PHYVer_MASK                                                                 0x00001FC0L
#define KPNP_SNPS0_KPNP_PHY_INFO__Technology_MASK                                                             0x000FE000L
#define KPNP_SNPS0_KPNP_PHY_INFO__Type_MASK                                                                   0x03F00000L
#define KPNP_SNPS0_KPNP_PHY_INFO__VendorID_MASK                                                               0xFC000000L
//KPNP_SNPS0_KPNP_LANE_ID
#define KPNP_SNPS0_KPNP_LANE_ID__NodeStartLane__SHIFT                                                         0x0
#define KPNP_SNPS0_KPNP_LANE_ID__NodeEndLane__SHIFT                                                           0x8
#define KPNP_SNPS0_KPNP_LANE_ID__NodeStartLane_MASK                                                           0x000000FFL
#define KPNP_SNPS0_KPNP_LANE_ID__NodeEndLane_MASK                                                             0x0000FF00L
//KPNP_SNPS0_KPNP_LANE_REQ_CONTROL
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT                                                     0x0
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT                                                     0x1
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT                                                     0x2
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT                                                     0x3
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT                                                     0x4
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT                                                     0x5
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT                                                     0x6
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT                                                     0x7
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK                                                       0x00000001L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK                                                       0x00000002L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK                                                       0x00000004L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK                                                       0x00000008L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK                                                       0x00000010L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK                                                       0x00000020L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK                                                       0x00000040L
#define KPNP_SNPS0_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK                                                       0x00000080L
//KPNP_SNPS0_KPNP_LANE_REQ_STATUS
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT                                                      0x0
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT                                                      0x1
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT                                                      0x2
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT                                                      0x3
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT                                                      0x4
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT                                                      0x5
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT                                                      0x6
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT                                                      0x7
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK                                                        0x00000001L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK                                                        0x00000002L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK                                                        0x00000004L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK                                                        0x00000008L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK                                                        0x00000010L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK                                                        0x00000020L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK                                                        0x00000040L
#define KPNP_SNPS0_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK                                                        0x00000080L
//KPNP_SNPS0_KPNP_PMA_CONTROL0
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT                                                      0x0
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT                                                   0x10
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT                                                   0x11
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT                                                   0x12
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT                                                   0x13
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT                                                   0x14
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT                                                   0x15
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT                                                   0x16
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT                                                   0x17
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__ref_use_pad_MASK                                                        0x00000001L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK                                                     0x00010000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK                                                     0x00020000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK                                                     0x00040000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK                                                     0x00080000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK                                                     0x00100000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK                                                     0x00200000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK                                                     0x00400000L
#define KPNP_SNPS0_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK                                                     0x00800000L
//KPNP_SNPS0_KPNP_PMA_CONTROL1
#define KPNP_SNPS0_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT                                                     0x0
#define KPNP_SNPS0_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT                                                    0x5
#define KPNP_SNPS0_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK                                                       0x0000001FL
#define KPNP_SNPS0_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK                                                      0x000000E0L
//KPNP_SNPS0_KPNP_PMA_CONTROL2
#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT                                               0x0
#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT                                                  0x1
#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT                                       0x2
#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Disable_MASK                                                 0x00000001L
#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Mode_MASK                                                    0x00000002L
#define KPNP_SNPS0_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK                                         0x0000001CL
//KPNP_SNPS0_KPNP_PHY_SOFT_RESET
#define KPNP_SNPS0_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT                                                 0x0
#define KPNP_SNPS0_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK                                                   0x00000001L
//KPNP_SNPS0_KPNP_LANE_SOFT_RESET
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT                                             0x0
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT                                             0x1
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT                                             0x2
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT                                             0x3
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT                                             0x4
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT                                             0x5
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT                                             0x6
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT                                             0x7
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK                                               0x00000001L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK                                               0x00000002L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK                                               0x00000004L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK                                               0x00000008L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK                                               0x00000010L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK                                               0x00000020L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK                                               0x00000040L
#define KPNP_SNPS0_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK                                               0x00000080L
//KPNP_SNPS0_REG_RST_CTRL
#define KPNP_SNPS0_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT                                          0x0
#define KPNP_SNPS0_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK                                            0x00000001L


// addressBlock: nbio_pipe_pcs_pcs_core0_dir
//PCS_PCIEX16_IP_IDENTITY
#define PCS_PCIEX16_IP_IDENTITY__IP_IDENTITY__SHIFT                                                           0x0
#define PCS_PCIEX16_IP_IDENTITY__IP_IDENTITY_MASK                                                             0xFFFFFFFFL
//PCS_PCIEX16_GLOBAL_CONTROL0
#define PCS_PCIEX16_GLOBAL_CONTROL0__InitHardware__SHIFT                                                      0x0
#define PCS_PCIEX16_GLOBAL_CONTROL0__InitComplete__SHIFT                                                      0x1
#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorCycle__SHIFT                                                   0x2
#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOnTime__SHIFT                                                  0x4
#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOnTime__SHIFT                            0xe
#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOffTime__SHIFT                           0xf
#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingTransitionTime__SHIFT                                      0x10
#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOffTime__SHIFT                                                 0x14
#define PCS_PCIEX16_GLOBAL_CONTROL0__InitHardware_MASK                                                        0x00000001L
#define PCS_PCIEX16_GLOBAL_CONTROL0__InitComplete_MASK                                                        0x00000002L
#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorCycle_MASK                                                     0x00000004L
#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOnTime_MASK                                                    0x00003FF0L
#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOnTime_MASK                              0x00004000L
#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingEnDuringEIDetectorOffTime_MASK                             0x00008000L
#define PCS_PCIEX16_GLOBAL_CONTROL0__VoltageDimmingTransitionTime_MASK                                        0x000F0000L
#define PCS_PCIEX16_GLOBAL_CONTROL0__EIDetectorOffTime_MASK                                                   0x3FF00000L
//PCS_PCIEX16_GLOBAL_CONTROL1
#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultPCLKFrequency__SHIFT                                              0x0
#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultMaximumLinkRate__SHIFT                                            0x2
#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLL__SHIFT                                                         0x4
#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLLAuto__SHIFT                                                     0x8
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxActivePowerGating__SHIFT                                          0x9
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxActivePowerGating__SHIFT                                          0xa
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxInactivePowerGating__SHIFT                                        0xb
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxInactivePowerGating__SHIFT                                        0xc
#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableTxSSClkGating__SHIFT                                               0xd
#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableMaxPClkGating__SHIFT                                               0xe
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS2__SHIFT                                                        0x10
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS3__SHIFT                                                        0x11
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS2__SHIFT                                                        0x12
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS3__SHIFT                                                        0x13
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowPLLShutdownRxPS2__SHIFT                                             0x15
#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveAbovePS4__SHIFT                                                 0x18
#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveInPS4__SHIFT                                                    0x19
#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableRxPS4__SHIFT                                                      0x1a
#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4__SHIFT                                                      0x1b
#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4inRxPS3__SHIFT                                               0x1c
#define PCS_PCIEX16_GLOBAL_CONTROL1__RemapSATAP6TOP5__SHIFT                                                   0x1d
#define PCS_PCIEX16_GLOBAL_CONTROL1__FarEndAnalogLoopbackEnable__SHIFT                                        0x1f
#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultPCLKFrequency_MASK                                                0x00000003L
#define PCS_PCIEX16_GLOBAL_CONTROL1__DefaultMaximumLinkRate_MASK                                              0x0000000CL
#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLL_MASK                                                           0x000000F0L
#define PCS_PCIEX16_GLOBAL_CONTROL1__MasterPLLAuto_MASK                                                       0x00000100L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxActivePowerGating_MASK                                            0x00000200L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxActivePowerGating_MASK                                            0x00000400L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxInactivePowerGating_MASK                                          0x00000800L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxInactivePowerGating_MASK                                          0x00001000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableTxSSClkGating_MASK                                                 0x00002000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__EnableMaxPClkGating_MASK                                                 0x00004000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS2_MASK                                                          0x00010000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowRxPS3_MASK                                                          0x00020000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS2_MASK                                                          0x00040000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowTxPS3_MASK                                                          0x00080000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__AllowPLLShutdownRxPS2_MASK                                               0x00200000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveAbovePS4_MASK                                                   0x01000000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__PLLActiveInPS4_MASK                                                      0x02000000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableRxPS4_MASK                                                        0x04000000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4_MASK                                                        0x08000000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__DisableTxPS4inRxPS3_MASK                                                 0x10000000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__RemapSATAP6TOP5_MASK                                                     0x20000000L
#define PCS_PCIEX16_GLOBAL_CONTROL1__FarEndAnalogLoopbackEnable_MASK                                          0x80000000L
//PCS_PCIEX16_GLOBAL_CONTROL2
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReceiverOntime__SHIFT                                           0x0
#define PCS_PCIEX16_GLOBAL_CONTROL2__ElasticFIFONominalHalfOffset__SHIFT                                      0xc
#define PCS_PCIEX16_GLOBAL_CONTROL2__AllowFrequencyVetting__SHIFT                                             0xe
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequency__SHIFT                                  0x10
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequencyStatus__SHIFT                            0x11
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYFifoInitWaitTime__SHIFT                                         0x12
#define PCS_PCIEX16_GLOBAL_CONTROL2__MinimumNumberofEISymbols__SHIFT                                          0x14
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReceiverOntime_MASK                                             0x000003FFL
#define PCS_PCIEX16_GLOBAL_CONTROL2__ElasticFIFONominalHalfOffset_MASK                                        0x00003000L
#define PCS_PCIEX16_GLOBAL_CONTROL2__AllowFrequencyVetting_MASK                                               0x00004000L
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequency_MASK                                    0x00010000L
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYReferenceClockFrequencyStatus_MASK                              0x00020000L
#define PCS_PCIEX16_GLOBAL_CONTROL2__SERDESPHYFifoInitWaitTime_MASK                                           0x000C0000L
#define PCS_PCIEX16_GLOBAL_CONTROL2__MinimumNumberofEISymbols_MASK                                            0x00300000L
//PCS_PCIEX16_GLOBAL_CONTROL3
#define PCS_PCIEX16_GLOBAL_CONTROL3__SERDESPHYPLLTransitionTime__SHIFT                                        0x0
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingTxRdy__SHIFT                                               0x10
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxRdy__SHIFT                                               0x11
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxStandbyRxRdy__SHIFT                                      0x12
#define PCS_PCIEX16_GLOBAL_CONTROL3__DisableMultiLaneBinding__SHIFT                                           0x13
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnClockSwitchRequest__SHIFT                                 0x14
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnGateUngatePCLKRequest__SHIFT                              0x18
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnSpeedChangeRequest__SHIFT                                 0x19
#define PCS_PCIEX16_GLOBAL_CONTROL3__SERDESPHYPLLTransitionTime_MASK                                          0x0000003FL
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingTxRdy_MASK                                                 0x00010000L
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxRdy_MASK                                                 0x00020000L
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowBypassingRxStandbyRxRdy_MASK                                        0x00040000L
#define PCS_PCIEX16_GLOBAL_CONTROL3__DisableMultiLaneBinding_MASK                                             0x00080000L
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnClockSwitchRequest_MASK                                   0x00100000L
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnGateUngatePCLKRequest_MASK                                0x01000000L
#define PCS_PCIEX16_GLOBAL_CONTROL3__AllowDummyAckOnSpeedChangeRequest_MASK                                   0x02000000L
//PCS_PCIEX16_GLOBAL_CONTROL4
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_EN__SHIFT                                                           0x0
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_TEST_MODE__SHIFT                                                    0x1
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_USER_PATTERN_TOGGLE__SHIFT                                          0x4
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_8BIT_SEL__SHIFT                                                     0x5
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_COMMA_NUM__SHIFT                                                    0x6
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LOCK_CNT__SHIFT                                                     0x8
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_FREERUN__SHIFT                                                      0xd
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_RATE__SHIFT                                                    0xe
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LANE_SELECT__SHIFT                                                  0x10
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_POLARITY_EN__SHIFT                                                  0x14
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_CLR__SHIFT                                                          0x15
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_WIDTH__SHIFT                                                   0x16
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_BYPASS_SYMALIGN__SHIFT                                              0x18
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_RESERVED__SHIFT                                                     0x19
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_EN_MASK                                                             0x00000001L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_TEST_MODE_MASK                                                      0x0000000EL
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_USER_PATTERN_TOGGLE_MASK                                            0x00000010L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_8BIT_SEL_MASK                                                       0x00000020L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_COMMA_NUM_MASK                                                      0x000000C0L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LOCK_CNT_MASK                                                       0x00001F00L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_FREERUN_MASK                                                        0x00002000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_RATE_MASK                                                      0x0000C000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_LANE_SELECT_MASK                                                    0x000F0000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_POLARITY_EN_MASK                                                    0x00100000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_CLR_MASK                                                            0x00200000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_DATA_WIDTH_MASK                                                     0x00C00000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_BYPASS_SYMALIGN_MASK                                                0x01000000L
#define PCS_PCIEX16_GLOBAL_CONTROL4__PRBS_RESERVED_MASK                                                       0xFE000000L
//PCS_PCIEX16_GLOBAL_CONTROL5
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_CHK_ERR_MASK__SHIFT                                                 0x0
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_LOCKED__SHIFT                                                       0x8
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_ERRSTAT__SHIFT                                                      0x10
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_BITCNT_DONE__SHIFT                                                  0x18
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_CHK_ERR_MASK_MASK                                                   0x000000FFL
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_LOCKED_MASK                                                         0x0000FF00L
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_ERRSTAT_MASK                                                        0x00FF0000L
#define PCS_PCIEX16_GLOBAL_CONTROL5__PRBS_BITCNT_DONE_MASK                                                    0xFF000000L
//PCS_PCIEX16_GLOBAL_CONTROL6
#define PCS_PCIEX16_GLOBAL_CONTROL6__PRBS_USER_PATTERN__SHIFT                                                 0x0
#define PCS_PCIEX16_GLOBAL_CONTROL6__PRBS_USER_PATTERN_MASK                                                   0x3FFFFFFFL
//PCS_PCIEX16_GLOBAL_CONTROL7
#define PCS_PCIEX16_GLOBAL_CONTROL7__PRBS_BITCNT__SHIFT                                                       0x0
#define PCS_PCIEX16_GLOBAL_CONTROL7__PRBS_BITCNT_MASK                                                         0xFFFFFFFFL
//PCS_PCIEX16_GLOBAL_CONTROL8
#define PCS_PCIEX16_GLOBAL_CONTROL8__PRBS_REGS_ERRCNT__SHIFT                                                  0x0
#define PCS_PCIEX16_GLOBAL_CONTROL8__PRBS_REGS_ERRCNT_MASK                                                    0xFFFFFFFFL
//PCS_PCIEX16_LANE0_CONTROL
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE0_CONTROL__PCS_PCIEX16_LANE0_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE1_CONTROL
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE1_CONTROL__PCS_PCIEX16_LANE1_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE2_CONTROL
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE2_CONTROL__PCS_PCIEX16_LANE2_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE3_CONTROL
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE3_CONTROL__PCS_PCIEX16_LANE3_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE4_CONTROL
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE4_CONTROL__PCS_PCIEX16_LANE4_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE5_CONTROL
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE5_CONTROL__PCS_PCIEX16_LANE5_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE6_CONTROL
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE6_CONTROL__PCS_PCIEX16_LANE6_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE7_CONTROL
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE7_CONTROL__PCS_PCIEX16_LANE7_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE8_CONTROL
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE8_CONTROL__PCS_PCIEX16_LANE8_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE9_CONTROL
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LogicalLinkNumber__SHIFT                         0x0
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_MasterPLLMask__SHIFT                             0x4
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_EnablePClkGating__SHIFT                          0x5
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LFPSPolarity__SHIFT                              0x10
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LogicalLinkNumber_MASK                           0x0000000FL
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_MasterPLLMask_MASK                               0x00000010L
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_EnablePClkGating_MASK                            0x00000020L
#define PCS_PCIEX16_LANE9_CONTROL__PCS_PCIEX16_LANE9_CONTROL_LFPSPolarity_MASK                                0x00010000L
//PCS_PCIEX16_LANE10_CONTROL
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LogicalLinkNumber__SHIFT                       0x0
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_MasterPLLMask__SHIFT                           0x4
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_EnablePClkGating__SHIFT                        0x5
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LFPSPolarity__SHIFT                            0x10
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LogicalLinkNumber_MASK                         0x0000000FL
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_MasterPLLMask_MASK                             0x00000010L
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_EnablePClkGating_MASK                          0x00000020L
#define PCS_PCIEX16_LANE10_CONTROL__PCS_PCIEX16_LANE10_CONTROL_LFPSPolarity_MASK                              0x00010000L
//PCS_PCIEX16_LANE11_CONTROL
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LogicalLinkNumber__SHIFT                       0x0
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_MasterPLLMask__SHIFT                           0x4
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_EnablePClkGating__SHIFT                        0x5
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LFPSPolarity__SHIFT                            0x10
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LogicalLinkNumber_MASK                         0x0000000FL
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_MasterPLLMask_MASK                             0x00000010L
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_EnablePClkGating_MASK                          0x00000020L
#define PCS_PCIEX16_LANE11_CONTROL__PCS_PCIEX16_LANE11_CONTROL_LFPSPolarity_MASK                              0x00010000L
//PCS_PCIEX16_LANE12_CONTROL
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LogicalLinkNumber__SHIFT                       0x0
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_MasterPLLMask__SHIFT                           0x4
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_EnablePClkGating__SHIFT                        0x5
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LFPSPolarity__SHIFT                            0x10
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LogicalLinkNumber_MASK                         0x0000000FL
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_MasterPLLMask_MASK                             0x00000010L
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_EnablePClkGating_MASK                          0x00000020L
#define PCS_PCIEX16_LANE12_CONTROL__PCS_PCIEX16_LANE12_CONTROL_LFPSPolarity_MASK                              0x00010000L
//PCS_PCIEX16_LANE13_CONTROL
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LogicalLinkNumber__SHIFT                       0x0
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_MasterPLLMask__SHIFT                           0x4
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_EnablePClkGating__SHIFT                        0x5
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LFPSPolarity__SHIFT                            0x10
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LogicalLinkNumber_MASK                         0x0000000FL
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_MasterPLLMask_MASK                             0x00000010L
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_EnablePClkGating_MASK                          0x00000020L
#define PCS_PCIEX16_LANE13_CONTROL__PCS_PCIEX16_LANE13_CONTROL_LFPSPolarity_MASK                              0x00010000L
//PCS_PCIEX16_LANE14_CONTROL
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LogicalLinkNumber__SHIFT                       0x0
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_MasterPLLMask__SHIFT                           0x4
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_EnablePClkGating__SHIFT                        0x5
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LFPSPolarity__SHIFT                            0x10
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LogicalLinkNumber_MASK                         0x0000000FL
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_MasterPLLMask_MASK                             0x00000010L
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_EnablePClkGating_MASK                          0x00000020L
#define PCS_PCIEX16_LANE14_CONTROL__PCS_PCIEX16_LANE14_CONTROL_LFPSPolarity_MASK                              0x00010000L
//PCS_PCIEX16_LANE15_CONTROL
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LogicalLinkNumber__SHIFT                       0x0
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_MasterPLLMask__SHIFT                           0x4
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_EnablePClkGating__SHIFT                        0x5
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LFPSPolarity__SHIFT                            0x10
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LogicalLinkNumber_MASK                         0x0000000FL
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_MasterPLLMask_MASK                             0x00000010L
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_EnablePClkGating_MASK                          0x00000020L
#define PCS_PCIEX16_LANE15_CONTROL__PCS_PCIEX16_LANE15_CONTROL_LFPSPolarity_MASK                              0x00010000L
//PCS_PCIEX16_GLOBAL_CONTROL9
#define PCS_PCIEX16_GLOBAL_CONTROL9__FullSwing__SHIFT                                                         0x0
#define PCS_PCIEX16_GLOBAL_CONTROL9__LowFrequency__SHIFT                                                      0x8
#define PCS_PCIEX16_GLOBAL_CONTROL9__FullSwing_MASK                                                           0x0000003FL
#define PCS_PCIEX16_GLOBAL_CONTROL9__LowFrequency_MASK                                                        0x00003F00L
//PCS_PCIEX16_GLOBAL_CONTROL10
#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqCheckSymbols__SHIFT                                           0x0
#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqTolerance__SHIFT                                              0x8
#define PCS_PCIEX16_GLOBAL_CONTROL10__AllowPointerSlipInterval__SHIFT                                         0x10
#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqCheckSymbols_MASK                                             0x0000007FL
#define PCS_PCIEX16_GLOBAL_CONTROL10__CoarseFreqTolerance_MASK                                                0x00001F00L
#define PCS_PCIEX16_GLOBAL_CONTROL10__AllowPointerSlipInterval_MASK                                           0x00FF0000L
//PCS_PCIEX16_GLOBAL_CONTROL11
#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingTimeout__SHIFT                                          0x0
#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingEn__SHIFT                                               0x9
#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRst__SHIFT                                                   0x10
#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRRC__SHIFT                                                   0x11
#define PCS_PCIEX16_GLOBAL_CONTROL11__ReceiverResetCycleEn__SHIFT                                             0x12
#define PCS_PCIEX16_GLOBAL_CONTROL11__SymAlignBypassEn__SHIFT                                                 0x13
#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingTimeout_MASK                                            0x000000FFL
#define PCS_PCIEX16_GLOBAL_CONTROL11__FrequencyVettingEn_MASK                                                 0x00000200L
#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRst_MASK                                                     0x00010000L
#define PCS_PCIEX16_GLOBAL_CONTROL11__ErrorActionRRC_MASK                                                     0x00020000L
#define PCS_PCIEX16_GLOBAL_CONTROL11__ReceiverResetCycleEn_MASK                                               0x00040000L
#define PCS_PCIEX16_GLOBAL_CONTROL11__SymAlignBypassEn_MASK                                                   0x00080000L
//PCS_PCIEX16_GLOBAL_CONTROL12
#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorLowThreshold_8b10b__SHIFT                               0x0
#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorHighThreshold_8b10b__SHIFT                              0x10
#define PCS_PCIEX16_GLOBAL_CONTROL12__DisparityErrorEn_8b10b__SHIFT                                           0x1e
#define PCS_PCIEX16_GLOBAL_CONTROL12__CodeErrorEn_8b10b__SHIFT                                                0x1f
#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorLowThreshold_8b10b_MASK                                 0x00000FFFL
#define PCS_PCIEX16_GLOBAL_CONTROL12__ErrorAccumulatorHighThreshold_8b10b_MASK                                0x0FFF0000L
#define PCS_PCIEX16_GLOBAL_CONTROL12__DisparityErrorEn_8b10b_MASK                                             0x40000000L
#define PCS_PCIEX16_GLOBAL_CONTROL12__CodeErrorEn_8b10b_MASK                                                  0x80000000L
//PCS_PCIEX16_GLOBAL_CONTROL13
#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorIncrement_8b10b__SHIFT                                  0x0
#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorDecrement_8b10b__SHIFT                                  0x8
#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorTimeout__SHIFT                                                     0x10
#define PCS_PCIEX16_GLOBAL_CONTROL13__Adjust_8b10b_AlignTimeout__SHIFT                                        0x1c
#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorIncrement_8b10b_MASK                                    0x0000001FL
#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorAccumulatorDecrement_8b10b_MASK                                    0x00001F00L
#define PCS_PCIEX16_GLOBAL_CONTROL13__ErrorTimeout_MASK                                                       0x00FF0000L
#define PCS_PCIEX16_GLOBAL_CONTROL13__Adjust_8b10b_AlignTimeout_MASK                                          0xF0000000L
//PCS_PCIEX16_GLOBAL_CONTROL14
#define PCS_PCIEX16_GLOBAL_CONTROL14__USBOnesZeros__SHIFT                                                     0x0
#define PCS_PCIEX16_GLOBAL_CONTROL14__EnableBCHCodeInSKPOS__SHIFT                                             0x5
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_Enable__SHIFT                                                      0x10
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DisparityErrorEnable__SHIFT                                        0x11
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DecodeErrorEnable__SHIFT                                           0x12
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LFSRErrorEnable__SHIFT                                             0x13
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LaneSelect__SHIFT                                                  0x14
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LastErrorCount__SHIFT                                              0x18
#define PCS_PCIEX16_GLOBAL_CONTROL14__USBOnesZeros_MASK                                                       0x0000001FL
#define PCS_PCIEX16_GLOBAL_CONTROL14__EnableBCHCodeInSKPOS_MASK                                               0x00000020L
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_Enable_MASK                                                        0x00010000L
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DisparityErrorEnable_MASK                                          0x00020000L
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_DecodeErrorEnable_MASK                                             0x00040000L
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LFSRErrorEnable_MASK                                               0x00080000L
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LaneSelect_MASK                                                    0x00F00000L
#define PCS_PCIEX16_GLOBAL_CONTROL14__BERT_LastErrorCount_MASK                                                0xFF000000L
//PCS_PCIEX16_GLOBAL_CONTROL15
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfMidPointMode1__SHIFT                              0x0
#define PCS_PCIEX16_GLOBAL_CONTROL15__OverrideElasticFIFOControlSettings__SHIFT                               0x5
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfHighThresholdMode1__SHIFT                         0x8
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticBufferProjectedWritePointerOffset__SHIFT                         0xd
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfLowThresholdMode1__SHIFT                          0x10
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalEmptyHighThresholdMode1__SHIFT                        0x18
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfMidPointMode1_MASK                                0x0000001FL
#define PCS_PCIEX16_GLOBAL_CONTROL15__OverrideElasticFIFOControlSettings_MASK                                 0x00000020L
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfHighThresholdMode1_MASK                           0x00001F00L
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticBufferProjectedWritePointerOffset_MASK                           0x0000E000L
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalHalfLowThresholdMode1_MASK                            0x001F0000L
#define PCS_PCIEX16_GLOBAL_CONTROL15__ElasticFIFONominalEmptyHighThresholdMode1_MASK                          0x1F000000L
//PCS_PCIEX16_GLOBAL_CONTROL16
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfMidPointMode2__SHIFT                              0x0
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfHighThresholdMode2__SHIFT                         0x8
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalLowHighThresholdMode2__SHIFT                          0x10
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalEmptyHighThresholdMode2__SHIFT                        0x18
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfMidPointMode2_MASK                                0x0000001FL
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalHalfHighThresholdMode2_MASK                           0x00001F00L
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalLowHighThresholdMode2_MASK                            0x001F0000L
#define PCS_PCIEX16_GLOBAL_CONTROL16__ElasticFIFONominalEmptyHighThresholdMode2_MASK                          0x1F000000L
//PCS_PCIEX16_GLOBAL_CONTROL17
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_CHK_ERR_MASK__SHIFT                                                0x0
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_LOCKED__SHIFT                                                      0x8
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_ERRSTAT__SHIFT                                                     0x10
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_BITCNT_DONE__SHIFT                                                 0x18
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_CHK_ERR_MASK_MASK                                                  0x000000FFL
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_LOCKED_MASK                                                        0x0000FF00L
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_ERRSTAT_MASK                                                       0x00FF0000L
#define PCS_PCIEX16_GLOBAL_CONTROL17__PRBS_BITCNT_DONE_MASK                                                   0xFF000000L


// addressBlock: nbio_pipe_pcs_pcs_pciex16_gaskt_pcs_pciex16_gaskt_dir
//PCS_GLOBAL_CONTROL17
#define PCS_GLOBAL_CONTROL17__refclk_range1__SHIFT                                                            0x0
#define PCS_GLOBAL_CONTROL17__refclk_div2_en1__SHIFT                                                          0x4
#define PCS_GLOBAL_CONTROL17__refclk_range1_MASK                                                              0x00000007L
#define PCS_GLOBAL_CONTROL17__refclk_div2_en1_MASK                                                            0x00000010L
//PCS_GLOBAL_CONTROL18
#define PCS_GLOBAL_CONTROL18__refclk_range2__SHIFT                                                            0x0
#define PCS_GLOBAL_CONTROL18__refclk_div2_en2__SHIFT                                                          0x4
#define PCS_GLOBAL_CONTROL18__refclk_range2_MASK                                                              0x00000007L
#define PCS_GLOBAL_CONTROL18__refclk_div2_en2_MASK                                                            0x00000010L
//PCS_GLOBAL_CONTROL19
#define PCS_GLOBAL_CONTROL19__mplla_multiplier1__SHIFT                                                        0x0
#define PCS_GLOBAL_CONTROL19__mplla_bandwidth1__SHIFT                                                         0x8
#define PCS_GLOBAL_CONTROL19__mplla_div8_clk_en1__SHIFT                                                       0x13
#define PCS_GLOBAL_CONTROL19__mplla_div10_clk_en1__SHIFT                                                      0x14
#define PCS_GLOBAL_CONTROL19__mplla_refclk_div2_en1__SHIFT                                                    0x18
#define PCS_GLOBAL_CONTROL19__mplla_init_cal_disable1__SHIFT                                                  0x1b
#define PCS_GLOBAL_CONTROL19__mplla_force_en1__SHIFT                                                          0x1c
#define PCS_GLOBAL_CONTROL19__mplla_multiplier1_MASK                                                          0x000000FFL
#define PCS_GLOBAL_CONTROL19__mplla_bandwidth1_MASK                                                           0x0007FF00L
#define PCS_GLOBAL_CONTROL19__mplla_div8_clk_en1_MASK                                                         0x00080000L
#define PCS_GLOBAL_CONTROL19__mplla_div10_clk_en1_MASK                                                        0x00100000L
#define PCS_GLOBAL_CONTROL19__mplla_refclk_div2_en1_MASK                                                      0x01000000L
#define PCS_GLOBAL_CONTROL19__mplla_init_cal_disable1_MASK                                                    0x08000000L
#define PCS_GLOBAL_CONTROL19__mplla_force_en1_MASK                                                            0x10000000L
//PCS_GLOBAL_CONTROL20
#define PCS_GLOBAL_CONTROL20__mplla_multiplier2__SHIFT                                                        0x0
#define PCS_GLOBAL_CONTROL20__mplla_bandwidth2__SHIFT                                                         0x8
#define PCS_GLOBAL_CONTROL20__mplla_div8_clk_en2__SHIFT                                                       0x13
#define PCS_GLOBAL_CONTROL20__mplla_div10_clk_en2__SHIFT                                                      0x14
#define PCS_GLOBAL_CONTROL20__mplla_refclk_div2_en2__SHIFT                                                    0x18
#define PCS_GLOBAL_CONTROL20__mplla_init_cal_disable2__SHIFT                                                  0x1b
#define PCS_GLOBAL_CONTROL20__mplla_force_en2__SHIFT                                                          0x1c
#define PCS_GLOBAL_CONTROL20__mplla_multiplier2_MASK                                                          0x000000FFL
#define PCS_GLOBAL_CONTROL20__mplla_bandwidth2_MASK                                                           0x0007FF00L
#define PCS_GLOBAL_CONTROL20__mplla_div8_clk_en2_MASK                                                         0x00080000L
#define PCS_GLOBAL_CONTROL20__mplla_div10_clk_en2_MASK                                                        0x00100000L
#define PCS_GLOBAL_CONTROL20__mplla_refclk_div2_en2_MASK                                                      0x01000000L
#define PCS_GLOBAL_CONTROL20__mplla_init_cal_disable2_MASK                                                    0x08000000L
#define PCS_GLOBAL_CONTROL20__mplla_force_en2_MASK                                                            0x10000000L
//PCS_GLOBAL_CONTROL21
#define PCS_GLOBAL_CONTROL21__mpllb_multiplier1__SHIFT                                                        0x0
#define PCS_GLOBAL_CONTROL21__mpllb_bandwidth1__SHIFT                                                         0x8
#define PCS_GLOBAL_CONTROL21__mpllb_div8_clk_en1__SHIFT                                                       0x13
#define PCS_GLOBAL_CONTROL21__mpllb_div10_clk_en1__SHIFT                                                      0x14
#define PCS_GLOBAL_CONTROL21__mpllb_refclk_div2_en1__SHIFT                                                    0x18
#define PCS_GLOBAL_CONTROL21__mpllb_init_cal_disable1__SHIFT                                                  0x1b
#define PCS_GLOBAL_CONTROL21__mpllb_force_en1__SHIFT                                                          0x1c
#define PCS_GLOBAL_CONTROL21__mpllb_multiplier1_MASK                                                          0x000000FFL
#define PCS_GLOBAL_CONTROL21__mpllb_bandwidth1_MASK                                                           0x0007FF00L
#define PCS_GLOBAL_CONTROL21__mpllb_div8_clk_en1_MASK                                                         0x00080000L
#define PCS_GLOBAL_CONTROL21__mpllb_div10_clk_en1_MASK                                                        0x00100000L
#define PCS_GLOBAL_CONTROL21__mpllb_refclk_div2_en1_MASK                                                      0x01000000L
#define PCS_GLOBAL_CONTROL21__mpllb_init_cal_disable1_MASK                                                    0x08000000L
#define PCS_GLOBAL_CONTROL21__mpllb_force_en1_MASK                                                            0x10000000L
//PCS_GLOBAL_CONTROL22
#define PCS_GLOBAL_CONTROL22__mpllb_multiplier2__SHIFT                                                        0x0
#define PCS_GLOBAL_CONTROL22__mpllb_bandwidth2__SHIFT                                                         0x8
#define PCS_GLOBAL_CONTROL22__mpllb_div8_clk_en2__SHIFT                                                       0x13
#define PCS_GLOBAL_CONTROL22__mpllb_div10_clk_en2__SHIFT                                                      0x14
#define PCS_GLOBAL_CONTROL22__mpllb_refclk_div2_en2__SHIFT                                                    0x18
#define PCS_GLOBAL_CONTROL22__mpllb_init_cal_disable2__SHIFT                                                  0x1b
#define PCS_GLOBAL_CONTROL22__mpllb_force_en2__SHIFT                                                          0x1c
#define PCS_GLOBAL_CONTROL22__mpllb_multiplier2_MASK                                                          0x000000FFL
#define PCS_GLOBAL_CONTROL22__mpllb_bandwidth2_MASK                                                           0x0007FF00L
#define PCS_GLOBAL_CONTROL22__mpllb_div8_clk_en2_MASK                                                         0x00080000L
#define PCS_GLOBAL_CONTROL22__mpllb_div10_clk_en2_MASK                                                        0x00100000L
#define PCS_GLOBAL_CONTROL22__mpllb_refclk_div2_en2_MASK                                                      0x01000000L
#define PCS_GLOBAL_CONTROL22__mpllb_init_cal_disable2_MASK                                                    0x08000000L
#define PCS_GLOBAL_CONTROL22__mpllb_force_en2_MASK                                                            0x10000000L
//PCS_GLOBAL_CONTROL23
#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl1__SHIFT                                                          0x0
#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl1__SHIFT                                                           0x4
#define PCS_GLOBAL_CONTROL23__txX_vboost_en1__SHIFT                                                           0x7
#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl2__SHIFT                                                          0x8
#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl2__SHIFT                                                           0xc
#define PCS_GLOBAL_CONTROL23__txX_vboost_en2__SHIFT                                                           0xf
#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl3__SHIFT                                                          0x10
#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl3__SHIFT                                                           0x14
#define PCS_GLOBAL_CONTROL23__txX_vboost_en3__SHIFT                                                           0x17
#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq1__SHIFT                                                     0x18
#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq2__SHIFT                                                     0x19
#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq3__SHIFT                                                     0x1a
#define PCS_GLOBAL_CONTROL23__rxX_cdr_ssc_en__SHIFT                                                           0x1b
#define PCS_GLOBAL_CONTROL23__rxX_term_acdc__SHIFT                                                            0x1c
#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl1_MASK                                                            0x0000000FL
#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl1_MASK                                                             0x00000070L
#define PCS_GLOBAL_CONTROL23__txX_vboost_en1_MASK                                                             0x00000080L
#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl2_MASK                                                            0x00000F00L
#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl2_MASK                                                             0x00007000L
#define PCS_GLOBAL_CONTROL23__txX_vboost_en2_MASK                                                             0x00008000L
#define PCS_GLOBAL_CONTROL23__txX_iboost_lvl3_MASK                                                            0x000F0000L
#define PCS_GLOBAL_CONTROL23__tx_vboost_lvl3_MASK                                                             0x00700000L
#define PCS_GLOBAL_CONTROL23__txX_vboost_en3_MASK                                                             0x00800000L
#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq1_MASK                                                       0x01000000L
#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq2_MASK                                                       0x02000000L
#define PCS_GLOBAL_CONTROL23__rxX_cdr_vco_lowfreq3_MASK                                                       0x04000000L
#define PCS_GLOBAL_CONTROL23__rxX_cdr_ssc_en_MASK                                                             0x08000000L
#define PCS_GLOBAL_CONTROL23__rxX_term_acdc_MASK                                                              0x10000000L
//PCS_GLOBAL_CONTROL24
#define PCS_GLOBAL_CONTROL24__rxX_eq_vga1_gain_gen1__SHIFT                                                    0x0
#define PCS_GLOBAL_CONTROL24__rxX_eq_vga2_gain_gen1__SHIFT                                                    0x4
#define PCS_GLOBAL_CONTROL24__rxX_eq_dfe_tap_gen1__SHIFT                                                      0x10
#define PCS_GLOBAL_CONTROL24__rxX_eq_att_lvl_gen1__SHIFT                                                      0x18
#define PCS_GLOBAL_CONTROL24__rxX_adapt_afe_en_gen1__SHIFT                                                    0x1c
#define PCS_GLOBAL_CONTROL24__rxX_adapt_dfe_en_gen1__SHIFT                                                    0x1d
#define PCS_GLOBAL_CONTROL24__rxX_eq_vga1_gain_gen1_MASK                                                      0x0000000FL
#define PCS_GLOBAL_CONTROL24__rxX_eq_vga2_gain_gen1_MASK                                                      0x000000F0L
#define PCS_GLOBAL_CONTROL24__rxX_eq_dfe_tap_gen1_MASK                                                        0x00FF0000L
#define PCS_GLOBAL_CONTROL24__rxX_eq_att_lvl_gen1_MASK                                                        0x07000000L
#define PCS_GLOBAL_CONTROL24__rxX_adapt_afe_en_gen1_MASK                                                      0x10000000L
#define PCS_GLOBAL_CONTROL24__rxX_adapt_dfe_en_gen1_MASK                                                      0x20000000L
//PCS_GLOBAL_CONTROL25
#define PCS_GLOBAL_CONTROL25__rxX_eq_vga1_gain_gen2__SHIFT                                                    0x0
#define PCS_GLOBAL_CONTROL25__rxX_eq_vga2_gain_gen2__SHIFT                                                    0x4
#define PCS_GLOBAL_CONTROL25__rxX_eq_dfe_tap_gen2__SHIFT                                                      0x10
#define PCS_GLOBAL_CONTROL25__rxX_eq_att_lvl_gen2__SHIFT                                                      0x18
#define PCS_GLOBAL_CONTROL25__rxX_adapt_afe_en_gen2__SHIFT                                                    0x1c
#define PCS_GLOBAL_CONTROL25__rxX_adapt_dfe_en_gen2__SHIFT                                                    0x1d
#define PCS_GLOBAL_CONTROL25__rxX_eq_vga1_gain_gen2_MASK                                                      0x0000000FL
#define PCS_GLOBAL_CONTROL25__rxX_eq_vga2_gain_gen2_MASK                                                      0x000000F0L
#define PCS_GLOBAL_CONTROL25__rxX_eq_dfe_tap_gen2_MASK                                                        0x00FF0000L
#define PCS_GLOBAL_CONTROL25__rxX_eq_att_lvl_gen2_MASK                                                        0x07000000L
#define PCS_GLOBAL_CONTROL25__rxX_adapt_afe_en_gen2_MASK                                                      0x10000000L
#define PCS_GLOBAL_CONTROL25__rxX_adapt_dfe_en_gen2_MASK                                                      0x20000000L
//PCS_GLOBAL_CONTROL26
#define PCS_GLOBAL_CONTROL26__rxX_eq_vga1_gain_gen3__SHIFT                                                    0x0
#define PCS_GLOBAL_CONTROL26__rxX_eq_vga2_gain_gen3__SHIFT                                                    0x4
#define PCS_GLOBAL_CONTROL26__rxX_eq_dfe_tap_gen3__SHIFT                                                      0x10
#define PCS_GLOBAL_CONTROL26__rxX_eq_att_lvl_gen3__SHIFT                                                      0x18
#define PCS_GLOBAL_CONTROL26__rxX_adapt_afe_en_gen3__SHIFT                                                    0x1c
#define PCS_GLOBAL_CONTROL26__rxX_adapt_dfe_en_gen3__SHIFT                                                    0x1d
#define PCS_GLOBAL_CONTROL26__rxX_eq_vga1_gain_gen3_MASK                                                      0x0000000FL
#define PCS_GLOBAL_CONTROL26__rxX_eq_vga2_gain_gen3_MASK                                                      0x000000F0L
#define PCS_GLOBAL_CONTROL26__rxX_eq_dfe_tap_gen3_MASK                                                        0x00FF0000L
#define PCS_GLOBAL_CONTROL26__rxX_eq_att_lvl_gen3_MASK                                                        0x07000000L
#define PCS_GLOBAL_CONTROL26__rxX_adapt_afe_en_gen3_MASK                                                      0x10000000L
#define PCS_GLOBAL_CONTROL26__rxX_adapt_dfe_en_gen3_MASK                                                      0x20000000L
//PCS_GLOBAL_CONTROL27
#define PCS_GLOBAL_CONTROL27__rxX_vco_ld_val1__SHIFT                                                          0x0
#define PCS_GLOBAL_CONTROL27__rxX_ref_ld_val1__SHIFT                                                          0x10
#define PCS_GLOBAL_CONTROL27__rx_vref_ctrl1__SHIFT                                                            0x18
#define PCS_GLOBAL_CONTROL27__rxX_vco_ld_val1_MASK                                                            0x00001FFFL
#define PCS_GLOBAL_CONTROL27__rxX_ref_ld_val1_MASK                                                            0x003F0000L
#define PCS_GLOBAL_CONTROL27__rx_vref_ctrl1_MASK                                                              0x1F000000L
//PCS_GLOBAL_CONTROL28
#define PCS_GLOBAL_CONTROL28__rxX_vco_ld_val2__SHIFT                                                          0x0
#define PCS_GLOBAL_CONTROL28__rxX_ref_ld_val2__SHIFT                                                          0x10
#define PCS_GLOBAL_CONTROL28__rx_vref_ctrl2__SHIFT                                                            0x18
#define PCS_GLOBAL_CONTROL28__rxX_vco_ld_val2_MASK                                                            0x00001FFFL
#define PCS_GLOBAL_CONTROL28__rxX_ref_ld_val2_MASK                                                            0x003F0000L
#define PCS_GLOBAL_CONTROL28__rx_vref_ctrl2_MASK                                                              0x1F000000L
//PCS_GLOBAL_CONTROL29
#define PCS_GLOBAL_CONTROL29__rxX_vco_ld_val3__SHIFT                                                          0x0
#define PCS_GLOBAL_CONTROL29__rxX_ref_ld_val3__SHIFT                                                          0x10
#define PCS_GLOBAL_CONTROL29__rx_vref_ctrl3__SHIFT                                                            0x18
#define PCS_GLOBAL_CONTROL29__rxX_vco_ld_val3_MASK                                                            0x00001FFFL
#define PCS_GLOBAL_CONTROL29__rxX_ref_ld_val3_MASK                                                            0x003F0000L
#define PCS_GLOBAL_CONTROL29__rx_vref_ctrl3_MASK                                                              0x1F000000L
//PCS_GLOBAL_CONTROL30
#define PCS_GLOBAL_CONTROL30__MPLLAInformationUpdate__SHIFT                                                   0x0
#define PCS_GLOBAL_CONTROL30__MPLLBInformationUpdate__SHIFT                                                   0x1
#define PCS_GLOBAL_CONTROL30__MPLLAControlOverride__SHIFT                                                     0x2
#define PCS_GLOBAL_CONTROL30__MPLLBControlOverride__SHIFT                                                     0x3
#define PCS_GLOBAL_CONTROL30__MPLLAControlOverrideValue__SHIFT                                                0x4
#define PCS_GLOBAL_CONTROL30__MPLLBControlOverrideValue__SHIFT                                                0x5
#define PCS_GLOBAL_CONTROL30__TransmitterInformationUpdate__SHIFT                                             0x6
#define PCS_GLOBAL_CONTROL30__ReceiverInformationUpdate__SHIFT                                                0x7
#define PCS_GLOBAL_CONTROL30__ReferenceClockInformationUpdate__SHIFT                                          0x8
#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverride__SHIFT                                            0x9
#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverrideValue__SHIFT                                       0xa
#define PCS_GLOBAL_CONTROL30__PowerManagerInterruptPriority__SHIFT                                            0xb
#define PCS_GLOBAL_CONTROL30__PLLSetupChangeAlgorithm__SHIFT                                                  0xc
#define PCS_GLOBAL_CONTROL30__MPLLAInformationUpdate_MASK                                                     0x00000001L
#define PCS_GLOBAL_CONTROL30__MPLLBInformationUpdate_MASK                                                     0x00000002L
#define PCS_GLOBAL_CONTROL30__MPLLAControlOverride_MASK                                                       0x00000004L
#define PCS_GLOBAL_CONTROL30__MPLLBControlOverride_MASK                                                       0x00000008L
#define PCS_GLOBAL_CONTROL30__MPLLAControlOverrideValue_MASK                                                  0x00000010L
#define PCS_GLOBAL_CONTROL30__MPLLBControlOverrideValue_MASK                                                  0x00000020L
#define PCS_GLOBAL_CONTROL30__TransmitterInformationUpdate_MASK                                               0x00000040L
#define PCS_GLOBAL_CONTROL30__ReceiverInformationUpdate_MASK                                                  0x00000080L
#define PCS_GLOBAL_CONTROL30__ReferenceClockInformationUpdate_MASK                                            0x00000100L
#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverride_MASK                                              0x00000200L
#define PCS_GLOBAL_CONTROL30__ReferenceClockControlOverrideValue_MASK                                         0x00000400L
#define PCS_GLOBAL_CONTROL30__PowerManagerInterruptPriority_MASK                                              0x00000800L
#define PCS_GLOBAL_CONTROL30__PLLSetupChangeAlgorithm_MASK                                                    0x00001000L
//PCS_STATUS1
#define PCS_STATUS1__LowPriorityInterrupt0Done__SHIFT                                                         0x0
#define PCS_STATUS1__HighPriorityInterrupt1Done__SHIFT                                                        0x1
#define PCS_STATUS1__LowPriorityInterrupt2Done__SHIFT                                                         0x2
#define PCS_STATUS1__LowPriorityInterrupt0Done_MASK                                                           0x00000001L
#define PCS_STATUS1__HighPriorityInterrupt1Done_MASK                                                          0x00000002L
#define PCS_STATUS1__LowPriorityInterrupt2Done_MASK                                                           0x00000004L
//PCS_LANE0_CNTRL1
#define PCS_LANE0_CNTRL1__rxX_los_threshold_lane0__SHIFT                                                      0x0
#define PCS_LANE0_CNTRL1__laneX_tx2rx_ser_lb_en_lane0__SHIFT                                                  0x10
#define PCS_LANE0_CNTRL1__rxX_los_threshold_lane0_MASK                                                        0x00000007L
#define PCS_LANE0_CNTRL1__laneX_tx2rx_ser_lb_en_lane0_MASK                                                    0x00010000L
//PCS_LANE1_CNTRL1
#define PCS_LANE1_CNTRL1__rxX_los_threshold_lane1__SHIFT                                                      0x0
#define PCS_LANE1_CNTRL1__laneX_tx2rx_ser_lb_en_lane1__SHIFT                                                  0x10
#define PCS_LANE1_CNTRL1__rxX_los_threshold_lane1_MASK                                                        0x00000007L
#define PCS_LANE1_CNTRL1__laneX_tx2rx_ser_lb_en_lane1_MASK                                                    0x00010000L
//PCS_LANE2_CNTRL1
#define PCS_LANE2_CNTRL1__rxX_los_threshold_lane2__SHIFT                                                      0x0
#define PCS_LANE2_CNTRL1__laneX_tx2rx_ser_lb_en_lane2__SHIFT                                                  0x10
#define PCS_LANE2_CNTRL1__rxX_los_threshold_lane2_MASK                                                        0x00000007L
#define PCS_LANE2_CNTRL1__laneX_tx2rx_ser_lb_en_lane2_MASK                                                    0x00010000L
//PCS_LANE3_CNTRL1
#define PCS_LANE3_CNTRL1__rxX_los_threshold_lane3__SHIFT                                                      0x0
#define PCS_LANE3_CNTRL1__laneX_tx2rx_ser_lb_en_lane3__SHIFT                                                  0x10
#define PCS_LANE3_CNTRL1__rxX_los_threshold_lane3_MASK                                                        0x00000007L
#define PCS_LANE3_CNTRL1__laneX_tx2rx_ser_lb_en_lane3_MASK                                                    0x00010000L
//PCS_LANE4_CNTRL1
#define PCS_LANE4_CNTRL1__rxX_los_threshold_lane4__SHIFT                                                      0x0
#define PCS_LANE4_CNTRL1__laneX_tx2rx_ser_lb_en_lane4__SHIFT                                                  0x10
#define PCS_LANE4_CNTRL1__rxX_los_threshold_lane4_MASK                                                        0x00000007L
#define PCS_LANE4_CNTRL1__laneX_tx2rx_ser_lb_en_lane4_MASK                                                    0x00010000L
//PCS_LANE5_CNTRL1
#define PCS_LANE5_CNTRL1__rxX_los_threshold_lane5__SHIFT                                                      0x0
#define PCS_LANE5_CNTRL1__laneX_tx2rx_ser_lb_en_lane5__SHIFT                                                  0x10
#define PCS_LANE5_CNTRL1__rxX_los_threshold_lane5_MASK                                                        0x00000007L
#define PCS_LANE5_CNTRL1__laneX_tx2rx_ser_lb_en_lane5_MASK                                                    0x00010000L
//PCS_LANE6_CNTRL1
#define PCS_LANE6_CNTRL1__rxX_los_threshold_lane6__SHIFT                                                      0x0
#define PCS_LANE6_CNTRL1__laneX_tx2rx_ser_lb_en_lane6__SHIFT                                                  0x10
#define PCS_LANE6_CNTRL1__rxX_los_threshold_lane6_MASK                                                        0x00000007L
#define PCS_LANE6_CNTRL1__laneX_tx2rx_ser_lb_en_lane6_MASK                                                    0x00010000L
//PCS_LANE7_CNTRL1
#define PCS_LANE7_CNTRL1__rxX_los_threshold_lane7__SHIFT                                                      0x0
#define PCS_LANE7_CNTRL1__laneX_tx2rx_ser_lb_en_lane7__SHIFT                                                  0x10
#define PCS_LANE7_CNTRL1__rxX_los_threshold_lane7_MASK                                                        0x00000007L
#define PCS_LANE7_CNTRL1__laneX_tx2rx_ser_lb_en_lane7_MASK                                                    0x00010000L
//PCS_LANE8_CNTRL1
#define PCS_LANE8_CNTRL1__rxX_los_threshold_lane8__SHIFT                                                      0x0
#define PCS_LANE8_CNTRL1__laneX_tx2rx_ser_lb_en_lane8__SHIFT                                                  0x10
#define PCS_LANE8_CNTRL1__rxX_los_threshold_lane8_MASK                                                        0x00000007L
#define PCS_LANE8_CNTRL1__laneX_tx2rx_ser_lb_en_lane8_MASK                                                    0x00010000L
//PCS_LANE9_CNTRL1
#define PCS_LANE9_CNTRL1__rxX_los_threshold_lane9__SHIFT                                                      0x0
#define PCS_LANE9_CNTRL1__laneX_tx2rx_ser_lb_en_lane9__SHIFT                                                  0x10
#define PCS_LANE9_CNTRL1__rxX_los_threshold_lane9_MASK                                                        0x00000007L
#define PCS_LANE9_CNTRL1__laneX_tx2rx_ser_lb_en_lane9_MASK                                                    0x00010000L
//PCS_LANE10_CNTRL1
#define PCS_LANE10_CNTRL1__rxX_los_threshold_lane10__SHIFT                                                    0x0
#define PCS_LANE10_CNTRL1__laneX_tx2rx_ser_lb_en_lane10__SHIFT                                                0x10
#define PCS_LANE10_CNTRL1__rxX_los_threshold_lane10_MASK                                                      0x00000007L
#define PCS_LANE10_CNTRL1__laneX_tx2rx_ser_lb_en_lane10_MASK                                                  0x00010000L
//PCS_LANE11_CNTRL1
#define PCS_LANE11_CNTRL1__rxX_los_threshold_lane11__SHIFT                                                    0x0
#define PCS_LANE11_CNTRL1__laneX_tx2rx_ser_lb_en_lane11__SHIFT                                                0x10
#define PCS_LANE11_CNTRL1__rxX_los_threshold_lane11_MASK                                                      0x00000007L
#define PCS_LANE11_CNTRL1__laneX_tx2rx_ser_lb_en_lane11_MASK                                                  0x00010000L
//PCS_LANE12_CNTRL1
#define PCS_LANE12_CNTRL1__rxX_los_threshold_lane12__SHIFT                                                    0x0
#define PCS_LANE12_CNTRL1__laneX_tx2rx_ser_lb_en_lane12__SHIFT                                                0x10
#define PCS_LANE12_CNTRL1__rxX_los_threshold_lane12_MASK                                                      0x00000007L
#define PCS_LANE12_CNTRL1__laneX_tx2rx_ser_lb_en_lane12_MASK                                                  0x00010000L
//PCS_LANE13_CNTRL1
#define PCS_LANE13_CNTRL1__rxX_los_threshold_lane13__SHIFT                                                    0x0
#define PCS_LANE13_CNTRL1__laneX_tx2rx_ser_lb_en_lane13__SHIFT                                                0x10
#define PCS_LANE13_CNTRL1__rxX_los_threshold_lane13_MASK                                                      0x00000007L
#define PCS_LANE13_CNTRL1__laneX_tx2rx_ser_lb_en_lane13_MASK                                                  0x00010000L
//PCS_LANE14_CNTRL1
#define PCS_LANE14_CNTRL1__rxX_los_threshold_lane14__SHIFT                                                    0x0
#define PCS_LANE14_CNTRL1__laneX_tx2rx_ser_lb_en_lane14__SHIFT                                                0x10
#define PCS_LANE14_CNTRL1__rxX_los_threshold_lane14_MASK                                                      0x00000007L
#define PCS_LANE14_CNTRL1__laneX_tx2rx_ser_lb_en_lane14_MASK                                                  0x00010000L
//PCS_LANE15_CNTRL1
#define PCS_LANE15_CNTRL1__rxX_los_threshold_lane15__SHIFT                                                    0x0
#define PCS_LANE15_CNTRL1__laneX_tx2rx_ser_lb_en_lane15__SHIFT                                                0x10
#define PCS_LANE15_CNTRL1__rxX_los_threshold_lane15_MASK                                                      0x00000007L
#define PCS_LANE15_CNTRL1__laneX_tx2rx_ser_lb_en_lane15_MASK                                                  0x00010000L
//PCS_LANE0_COEFF1
#define PCS_LANE0_COEFF1__TxCoefficientPreCursor_lane0_gen1__SHIFT                                            0x0
#define PCS_LANE0_COEFF1__TxCoefficientMainCursor_lane0_gen1__SHIFT                                           0x8
#define PCS_LANE0_COEFF1__TxCoefficientPostCursor_lane0_gen1__SHIFT                                           0x10
#define PCS_LANE0_COEFF1__rxX_eq_ctle_boost_lane0_gen1__SHIFT                                                 0x18
#define PCS_LANE0_COEFF1__rxX_eq_ctle_pole_lane0_gen1__SHIFT                                                  0x1d
#define PCS_LANE0_COEFF1__TxCoefficientPreCursor_lane0_gen1_MASK                                              0x0000003FL
#define PCS_LANE0_COEFF1__TxCoefficientMainCursor_lane0_gen1_MASK                                             0x00003F00L
#define PCS_LANE0_COEFF1__TxCoefficientPostCursor_lane0_gen1_MASK                                             0x003F0000L
#define PCS_LANE0_COEFF1__rxX_eq_ctle_boost_lane0_gen1_MASK                                                   0x1F000000L
#define PCS_LANE0_COEFF1__rxX_eq_ctle_pole_lane0_gen1_MASK                                                    0xE0000000L
//PCS_LANE1_COEFF1
#define PCS_LANE1_COEFF1__TxCoefficientPreCursor_lane1_gen1__SHIFT                                            0x0
#define PCS_LANE1_COEFF1__TxCoefficientMainCursor_lane1_gen1__SHIFT                                           0x8
#define PCS_LANE1_COEFF1__TxCoefficientPostCursor_lane1_gen1__SHIFT                                           0x10
#define PCS_LANE1_COEFF1__rxX_eq_ctle_boost_lane1_gen1__SHIFT                                                 0x18
#define PCS_LANE1_COEFF1__rxX_eq_ctle_pole_lane1_gen1__SHIFT                                                  0x1d
#define PCS_LANE1_COEFF1__TxCoefficientPreCursor_lane1_gen1_MASK                                              0x0000003FL
#define PCS_LANE1_COEFF1__TxCoefficientMainCursor_lane1_gen1_MASK                                             0x00003F00L
#define PCS_LANE1_COEFF1__TxCoefficientPostCursor_lane1_gen1_MASK                                             0x003F0000L
#define PCS_LANE1_COEFF1__rxX_eq_ctle_boost_lane1_gen1_MASK                                                   0x1F000000L
#define PCS_LANE1_COEFF1__rxX_eq_ctle_pole_lane1_gen1_MASK                                                    0xE0000000L
//PCS_LANE2_COEFF1
#define PCS_LANE2_COEFF1__TxCoefficientPreCursor_lane2_gen1__SHIFT                                            0x0
#define PCS_LANE2_COEFF1__TxCoefficientMainCursor_lane2_gen1__SHIFT                                           0x8
#define PCS_LANE2_COEFF1__TxCoefficientPostCursor_lane2_gen1__SHIFT                                           0x10
#define PCS_LANE2_COEFF1__rxX_eq_ctle_boost_lane2_gen1__SHIFT                                                 0x18
#define PCS_LANE2_COEFF1__rxX_eq_ctle_pole_lane2_gen1__SHIFT                                                  0x1d
#define PCS_LANE2_COEFF1__TxCoefficientPreCursor_lane2_gen1_MASK                                              0x0000003FL
#define PCS_LANE2_COEFF1__TxCoefficientMainCursor_lane2_gen1_MASK                                             0x00003F00L
#define PCS_LANE2_COEFF1__TxCoefficientPostCursor_lane2_gen1_MASK                                             0x003F0000L
#define PCS_LANE2_COEFF1__rxX_eq_ctle_boost_lane2_gen1_MASK                                                   0x1F000000L
#define PCS_LANE2_COEFF1__rxX_eq_ctle_pole_lane2_gen1_MASK                                                    0xE0000000L
//PCS_LANE3_COEFF1
#define PCS_LANE3_COEFF1__TxCoefficientPreCursor_lane3_gen1__SHIFT                                            0x0
#define PCS_LANE3_COEFF1__TxCoefficientMainCursor_lane3_gen1__SHIFT                                           0x8
#define PCS_LANE3_COEFF1__TxCoefficientPostCursor_lane3_gen1__SHIFT                                           0x10
#define PCS_LANE3_COEFF1__rxX_eq_ctle_boost_lane3_gen1__SHIFT                                                 0x18
#define PCS_LANE3_COEFF1__rxX_eq_ctle_pole_lane3_gen1__SHIFT                                                  0x1d
#define PCS_LANE3_COEFF1__TxCoefficientPreCursor_lane3_gen1_MASK                                              0x0000003FL
#define PCS_LANE3_COEFF1__TxCoefficientMainCursor_lane3_gen1_MASK                                             0x00003F00L
#define PCS_LANE3_COEFF1__TxCoefficientPostCursor_lane3_gen1_MASK                                             0x003F0000L
#define PCS_LANE3_COEFF1__rxX_eq_ctle_boost_lane3_gen1_MASK                                                   0x1F000000L
#define PCS_LANE3_COEFF1__rxX_eq_ctle_pole_lane3_gen1_MASK                                                    0xE0000000L
//PCS_LANE4_COEFF1
#define PCS_LANE4_COEFF1__TxCoefficientPreCursor_lane4_gen1__SHIFT                                            0x0
#define PCS_LANE4_COEFF1__TxCoefficientMainCursor_lane4_gen1__SHIFT                                           0x8
#define PCS_LANE4_COEFF1__TxCoefficientPostCursor_lane4_gen1__SHIFT                                           0x10
#define PCS_LANE4_COEFF1__rxX_eq_ctle_boost_lane4_gen1__SHIFT                                                 0x18
#define PCS_LANE4_COEFF1__rxX_eq_ctle_pole_lane4_gen1__SHIFT                                                  0x1d
#define PCS_LANE4_COEFF1__TxCoefficientPreCursor_lane4_gen1_MASK                                              0x0000003FL
#define PCS_LANE4_COEFF1__TxCoefficientMainCursor_lane4_gen1_MASK                                             0x00003F00L
#define PCS_LANE4_COEFF1__TxCoefficientPostCursor_lane4_gen1_MASK                                             0x003F0000L
#define PCS_LANE4_COEFF1__rxX_eq_ctle_boost_lane4_gen1_MASK                                                   0x1F000000L
#define PCS_LANE4_COEFF1__rxX_eq_ctle_pole_lane4_gen1_MASK                                                    0xE0000000L
//PCS_LANE5_COEFF1
#define PCS_LANE5_COEFF1__TxCoefficientPreCursor_lane5_gen1__SHIFT                                            0x0
#define PCS_LANE5_COEFF1__TxCoefficientMainCursor_lane5_gen1__SHIFT                                           0x8
#define PCS_LANE5_COEFF1__TxCoefficientPostCursor_lane5_gen1__SHIFT                                           0x10
#define PCS_LANE5_COEFF1__rxX_eq_ctle_boost_lane5_gen1__SHIFT                                                 0x18
#define PCS_LANE5_COEFF1__rxX_eq_ctle_pole_lane5_gen1__SHIFT                                                  0x1d
#define PCS_LANE5_COEFF1__TxCoefficientPreCursor_lane5_gen1_MASK                                              0x0000003FL
#define PCS_LANE5_COEFF1__TxCoefficientMainCursor_lane5_gen1_MASK                                             0x00003F00L
#define PCS_LANE5_COEFF1__TxCoefficientPostCursor_lane5_gen1_MASK                                             0x003F0000L
#define PCS_LANE5_COEFF1__rxX_eq_ctle_boost_lane5_gen1_MASK                                                   0x1F000000L
#define PCS_LANE5_COEFF1__rxX_eq_ctle_pole_lane5_gen1_MASK                                                    0xE0000000L
//PCS_LANE6_COEFF1
#define PCS_LANE6_COEFF1__TxCoefficientPreCursor_lane6_gen1__SHIFT                                            0x0
#define PCS_LANE6_COEFF1__TxCoefficientMainCursor_lane6_gen1__SHIFT                                           0x8
#define PCS_LANE6_COEFF1__TxCoefficientPostCursor_lane6_gen1__SHIFT                                           0x10
#define PCS_LANE6_COEFF1__rxX_eq_ctle_boost_lane6_gen1__SHIFT                                                 0x18
#define PCS_LANE6_COEFF1__rxX_eq_ctle_pole_lane6_gen1__SHIFT                                                  0x1d
#define PCS_LANE6_COEFF1__TxCoefficientPreCursor_lane6_gen1_MASK                                              0x0000003FL
#define PCS_LANE6_COEFF1__TxCoefficientMainCursor_lane6_gen1_MASK                                             0x00003F00L
#define PCS_LANE6_COEFF1__TxCoefficientPostCursor_lane6_gen1_MASK                                             0x003F0000L
#define PCS_LANE6_COEFF1__rxX_eq_ctle_boost_lane6_gen1_MASK                                                   0x1F000000L
#define PCS_LANE6_COEFF1__rxX_eq_ctle_pole_lane6_gen1_MASK                                                    0xE0000000L
//PCS_LANE7_COEFF1
#define PCS_LANE7_COEFF1__TxCoefficientPreCursor_lane7_gen1__SHIFT                                            0x0
#define PCS_LANE7_COEFF1__TxCoefficientMainCursor_lane7_gen1__SHIFT                                           0x8
#define PCS_LANE7_COEFF1__TxCoefficientPostCursor_lane7_gen1__SHIFT                                           0x10
#define PCS_LANE7_COEFF1__rxX_eq_ctle_boost_lane7_gen1__SHIFT                                                 0x18
#define PCS_LANE7_COEFF1__rxX_eq_ctle_pole_lane7_gen1__SHIFT                                                  0x1d
#define PCS_LANE7_COEFF1__TxCoefficientPreCursor_lane7_gen1_MASK                                              0x0000003FL
#define PCS_LANE7_COEFF1__TxCoefficientMainCursor_lane7_gen1_MASK                                             0x00003F00L
#define PCS_LANE7_COEFF1__TxCoefficientPostCursor_lane7_gen1_MASK                                             0x003F0000L
#define PCS_LANE7_COEFF1__rxX_eq_ctle_boost_lane7_gen1_MASK                                                   0x1F000000L
#define PCS_LANE7_COEFF1__rxX_eq_ctle_pole_lane7_gen1_MASK                                                    0xE0000000L
//PCS_LANE8_COEFF1
#define PCS_LANE8_COEFF1__TxCoefficientPreCursor_lane8_gen1__SHIFT                                            0x0
#define PCS_LANE8_COEFF1__TxCoefficientMainCursor_lane8_gen1__SHIFT                                           0x8
#define PCS_LANE8_COEFF1__TxCoefficientPostCursor_lane8_gen1__SHIFT                                           0x10
#define PCS_LANE8_COEFF1__rxX_eq_ctle_boost_lane8_gen1__SHIFT                                                 0x18
#define PCS_LANE8_COEFF1__rxX_eq_ctle_pole_lane8_gen1__SHIFT                                                  0x1d
#define PCS_LANE8_COEFF1__TxCoefficientPreCursor_lane8_gen1_MASK                                              0x0000003FL
#define PCS_LANE8_COEFF1__TxCoefficientMainCursor_lane8_gen1_MASK                                             0x00003F00L
#define PCS_LANE8_COEFF1__TxCoefficientPostCursor_lane8_gen1_MASK                                             0x003F0000L
#define PCS_LANE8_COEFF1__rxX_eq_ctle_boost_lane8_gen1_MASK                                                   0x1F000000L
#define PCS_LANE8_COEFF1__rxX_eq_ctle_pole_lane8_gen1_MASK                                                    0xE0000000L
//PCS_LANE9_COEFF1
#define PCS_LANE9_COEFF1__TxCoefficientPreCursor_lane9_gen1__SHIFT                                            0x0
#define PCS_LANE9_COEFF1__TxCoefficientMainCursor_lane9_gen1__SHIFT                                           0x8
#define PCS_LANE9_COEFF1__TxCoefficientPostCursor_lane9_gen1__SHIFT                                           0x10
#define PCS_LANE9_COEFF1__rxX_eq_ctle_boost_lane9_gen1__SHIFT                                                 0x18
#define PCS_LANE9_COEFF1__rxX_eq_ctle_pole_lane9_gen1__SHIFT                                                  0x1d
#define PCS_LANE9_COEFF1__TxCoefficientPreCursor_lane9_gen1_MASK                                              0x0000003FL
#define PCS_LANE9_COEFF1__TxCoefficientMainCursor_lane9_gen1_MASK                                             0x00003F00L
#define PCS_LANE9_COEFF1__TxCoefficientPostCursor_lane9_gen1_MASK                                             0x003F0000L
#define PCS_LANE9_COEFF1__rxX_eq_ctle_boost_lane9_gen1_MASK                                                   0x1F000000L
#define PCS_LANE9_COEFF1__rxX_eq_ctle_pole_lane9_gen1_MASK                                                    0xE0000000L
//PCS_LANE10_COEFF1
#define PCS_LANE10_COEFF1__TxCoefficientPreCursor_lane10_gen1__SHIFT                                          0x0
#define PCS_LANE10_COEFF1__TxCoefficientMainCursor_lane10_gen1__SHIFT                                         0x8
#define PCS_LANE10_COEFF1__TxCoefficientPostCursor_lane10_gen1__SHIFT                                         0x10
#define PCS_LANE10_COEFF1__rxX_eq_ctle_boost_lane10_gen1__SHIFT                                               0x18
#define PCS_LANE10_COEFF1__rxX_eq_ctle_pole_lane10_gen1__SHIFT                                                0x1d
#define PCS_LANE10_COEFF1__TxCoefficientPreCursor_lane10_gen1_MASK                                            0x0000003FL
#define PCS_LANE10_COEFF1__TxCoefficientMainCursor_lane10_gen1_MASK                                           0x00003F00L
#define PCS_LANE10_COEFF1__TxCoefficientPostCursor_lane10_gen1_MASK                                           0x003F0000L
#define PCS_LANE10_COEFF1__rxX_eq_ctle_boost_lane10_gen1_MASK                                                 0x1F000000L
#define PCS_LANE10_COEFF1__rxX_eq_ctle_pole_lane10_gen1_MASK                                                  0xE0000000L
//PCS_LANE11_COEFF1
#define PCS_LANE11_COEFF1__TxCoefficientPreCursor_lane11_gen1__SHIFT                                          0x0
#define PCS_LANE11_COEFF1__TxCoefficientMainCursor_lane11_gen1__SHIFT                                         0x8
#define PCS_LANE11_COEFF1__TxCoefficientPostCursor_lane11_gen1__SHIFT                                         0x10
#define PCS_LANE11_COEFF1__rxX_eq_ctle_boost_lane11_gen1__SHIFT                                               0x18
#define PCS_LANE11_COEFF1__rxX_eq_ctle_pole_lane11_gen1__SHIFT                                                0x1d
#define PCS_LANE11_COEFF1__TxCoefficientPreCursor_lane11_gen1_MASK                                            0x0000003FL
#define PCS_LANE11_COEFF1__TxCoefficientMainCursor_lane11_gen1_MASK                                           0x00003F00L
#define PCS_LANE11_COEFF1__TxCoefficientPostCursor_lane11_gen1_MASK                                           0x003F0000L
#define PCS_LANE11_COEFF1__rxX_eq_ctle_boost_lane11_gen1_MASK                                                 0x1F000000L
#define PCS_LANE11_COEFF1__rxX_eq_ctle_pole_lane11_gen1_MASK                                                  0xE0000000L
//PCS_LANE12_COEFF1
#define PCS_LANE12_COEFF1__TxCoefficientPreCursor_lane12_gen1__SHIFT                                          0x0
#define PCS_LANE12_COEFF1__TxCoefficientMainCursor_lane12_gen1__SHIFT                                         0x8
#define PCS_LANE12_COEFF1__TxCoefficientPostCursor_lane12_gen1__SHIFT                                         0x10
#define PCS_LANE12_COEFF1__rxX_eq_ctle_boost_lane12_gen1__SHIFT                                               0x18
#define PCS_LANE12_COEFF1__rxX_eq_ctle_pole_lane12_gen1__SHIFT                                                0x1d
#define PCS_LANE12_COEFF1__TxCoefficientPreCursor_lane12_gen1_MASK                                            0x0000003FL
#define PCS_LANE12_COEFF1__TxCoefficientMainCursor_lane12_gen1_MASK                                           0x00003F00L
#define PCS_LANE12_COEFF1__TxCoefficientPostCursor_lane12_gen1_MASK                                           0x003F0000L
#define PCS_LANE12_COEFF1__rxX_eq_ctle_boost_lane12_gen1_MASK                                                 0x1F000000L
#define PCS_LANE12_COEFF1__rxX_eq_ctle_pole_lane12_gen1_MASK                                                  0xE0000000L
//PCS_LANE13_COEFF1
#define PCS_LANE13_COEFF1__TxCoefficientPreCursor_lane13_gen1__SHIFT                                          0x0
#define PCS_LANE13_COEFF1__TxCoefficientMainCursor_lane13_gen1__SHIFT                                         0x8
#define PCS_LANE13_COEFF1__TxCoefficientPostCursor_lane13_gen1__SHIFT                                         0x10
#define PCS_LANE13_COEFF1__rxX_eq_ctle_boost_lane13_gen1__SHIFT                                               0x18
#define PCS_LANE13_COEFF1__rxX_eq_ctle_pole_lane13_gen1__SHIFT                                                0x1d
#define PCS_LANE13_COEFF1__TxCoefficientPreCursor_lane13_gen1_MASK                                            0x0000003FL
#define PCS_LANE13_COEFF1__TxCoefficientMainCursor_lane13_gen1_MASK                                           0x00003F00L
#define PCS_LANE13_COEFF1__TxCoefficientPostCursor_lane13_gen1_MASK                                           0x003F0000L
#define PCS_LANE13_COEFF1__rxX_eq_ctle_boost_lane13_gen1_MASK                                                 0x1F000000L
#define PCS_LANE13_COEFF1__rxX_eq_ctle_pole_lane13_gen1_MASK                                                  0xE0000000L
//PCS_LANE14_COEFF1
#define PCS_LANE14_COEFF1__TxCoefficientPreCursor_lane14_gen1__SHIFT                                          0x0
#define PCS_LANE14_COEFF1__TxCoefficientMainCursor_lane14_gen1__SHIFT                                         0x8
#define PCS_LANE14_COEFF1__TxCoefficientPostCursor_lane14_gen1__SHIFT                                         0x10
#define PCS_LANE14_COEFF1__rxX_eq_ctle_boost_lane14_gen1__SHIFT                                               0x18
#define PCS_LANE14_COEFF1__rxX_eq_ctle_pole_lane14_gen1__SHIFT                                                0x1d
#define PCS_LANE14_COEFF1__TxCoefficientPreCursor_lane14_gen1_MASK                                            0x0000003FL
#define PCS_LANE14_COEFF1__TxCoefficientMainCursor_lane14_gen1_MASK                                           0x00003F00L
#define PCS_LANE14_COEFF1__TxCoefficientPostCursor_lane14_gen1_MASK                                           0x003F0000L
#define PCS_LANE14_COEFF1__rxX_eq_ctle_boost_lane14_gen1_MASK                                                 0x1F000000L
#define PCS_LANE14_COEFF1__rxX_eq_ctle_pole_lane14_gen1_MASK                                                  0xE0000000L
//PCS_LANE15_COEFF1
#define PCS_LANE15_COEFF1__TxCoefficientPreCursor_lane15_gen1__SHIFT                                          0x0
#define PCS_LANE15_COEFF1__TxCoefficientMainCursor_lane15_gen1__SHIFT                                         0x8
#define PCS_LANE15_COEFF1__TxCoefficientPostCursor_lane15_gen1__SHIFT                                         0x10
#define PCS_LANE15_COEFF1__rxX_eq_ctle_boost_lane15_gen1__SHIFT                                               0x18
#define PCS_LANE15_COEFF1__rxX_eq_ctle_pole_lane15_gen1__SHIFT                                                0x1d
#define PCS_LANE15_COEFF1__TxCoefficientPreCursor_lane15_gen1_MASK                                            0x0000003FL
#define PCS_LANE15_COEFF1__TxCoefficientMainCursor_lane15_gen1_MASK                                           0x00003F00L
#define PCS_LANE15_COEFF1__TxCoefficientPostCursor_lane15_gen1_MASK                                           0x003F0000L
#define PCS_LANE15_COEFF1__rxX_eq_ctle_boost_lane15_gen1_MASK                                                 0x1F000000L
#define PCS_LANE15_COEFF1__rxX_eq_ctle_pole_lane15_gen1_MASK                                                  0xE0000000L
//PCS_LANE0_COEFF2
#define PCS_LANE0_COEFF2__TxCoefficientPreCursor_lane0_gen2__SHIFT                                            0x0
#define PCS_LANE0_COEFF2__TxCoefficientMainCursor_lane0_gen2__SHIFT                                           0x8
#define PCS_LANE0_COEFF2__TxCoefficientPostCursor_lane0_gen2__SHIFT                                           0x10
#define PCS_LANE0_COEFF2__rxX_eq_ctle_boost_lane0_gen2__SHIFT                                                 0x18
#define PCS_LANE0_COEFF2__rxX_eq_ctle_pole_lane0_gen2__SHIFT                                                  0x1d
#define PCS_LANE0_COEFF2__TxCoefficientPreCursor_lane0_gen2_MASK                                              0x0000003FL
#define PCS_LANE0_COEFF2__TxCoefficientMainCursor_lane0_gen2_MASK                                             0x00003F00L
#define PCS_LANE0_COEFF2__TxCoefficientPostCursor_lane0_gen2_MASK                                             0x003F0000L
#define PCS_LANE0_COEFF2__rxX_eq_ctle_boost_lane0_gen2_MASK                                                   0x1F000000L
#define PCS_LANE0_COEFF2__rxX_eq_ctle_pole_lane0_gen2_MASK                                                    0xE0000000L
//PCS_LANE1_COEFF2
#define PCS_LANE1_COEFF2__TxCoefficientPreCursor_lane1_gen2__SHIFT                                            0x0
#define PCS_LANE1_COEFF2__TxCoefficientMainCursor_lane1_gen2__SHIFT                                           0x8
#define PCS_LANE1_COEFF2__TxCoefficientPostCursor_lane1_gen2__SHIFT                                           0x10
#define PCS_LANE1_COEFF2__rxX_eq_ctle_boost_lane1_gen2__SHIFT                                                 0x18
#define PCS_LANE1_COEFF2__rxX_eq_ctle_pole_lane1_gen2__SHIFT                                                  0x1d
#define PCS_LANE1_COEFF2__TxCoefficientPreCursor_lane1_gen2_MASK                                              0x0000003FL
#define PCS_LANE1_COEFF2__TxCoefficientMainCursor_lane1_gen2_MASK                                             0x00003F00L
#define PCS_LANE1_COEFF2__TxCoefficientPostCursor_lane1_gen2_MASK                                             0x003F0000L
#define PCS_LANE1_COEFF2__rxX_eq_ctle_boost_lane1_gen2_MASK                                                   0x1F000000L
#define PCS_LANE1_COEFF2__rxX_eq_ctle_pole_lane1_gen2_MASK                                                    0xE0000000L
//PCS_LANE2_COEFF2
#define PCS_LANE2_COEFF2__TxCoefficientPreCursor_lane2_gen2__SHIFT                                            0x0
#define PCS_LANE2_COEFF2__TxCoefficientMainCursor_lane2_gen2__SHIFT                                           0x8
#define PCS_LANE2_COEFF2__TxCoefficientPostCursor_lane2_gen2__SHIFT                                           0x10
#define PCS_LANE2_COEFF2__rxX_eq_ctle_boost_lane2_gen2__SHIFT                                                 0x18
#define PCS_LANE2_COEFF2__rxX_eq_ctle_pole_lane2_gen2__SHIFT                                                  0x1d
#define PCS_LANE2_COEFF2__TxCoefficientPreCursor_lane2_gen2_MASK                                              0x0000003FL
#define PCS_LANE2_COEFF2__TxCoefficientMainCursor_lane2_gen2_MASK                                             0x00003F00L
#define PCS_LANE2_COEFF2__TxCoefficientPostCursor_lane2_gen2_MASK                                             0x003F0000L
#define PCS_LANE2_COEFF2__rxX_eq_ctle_boost_lane2_gen2_MASK                                                   0x1F000000L
#define PCS_LANE2_COEFF2__rxX_eq_ctle_pole_lane2_gen2_MASK                                                    0xE0000000L
//PCS_LANE3_COEFF2
#define PCS_LANE3_COEFF2__TxCoefficientPreCursor_lane3_gen2__SHIFT                                            0x0
#define PCS_LANE3_COEFF2__TxCoefficientMainCursor_lane3_gen2__SHIFT                                           0x8
#define PCS_LANE3_COEFF2__TxCoefficientPostCursor_lane3_gen2__SHIFT                                           0x10
#define PCS_LANE3_COEFF2__rxX_eq_ctle_boost_lane3_gen2__SHIFT                                                 0x18
#define PCS_LANE3_COEFF2__rxX_eq_ctle_pole_lane3_gen2__SHIFT                                                  0x1d
#define PCS_LANE3_COEFF2__TxCoefficientPreCursor_lane3_gen2_MASK                                              0x0000003FL
#define PCS_LANE3_COEFF2__TxCoefficientMainCursor_lane3_gen2_MASK                                             0x00003F00L
#define PCS_LANE3_COEFF2__TxCoefficientPostCursor_lane3_gen2_MASK                                             0x003F0000L
#define PCS_LANE3_COEFF2__rxX_eq_ctle_boost_lane3_gen2_MASK                                                   0x1F000000L
#define PCS_LANE3_COEFF2__rxX_eq_ctle_pole_lane3_gen2_MASK                                                    0xE0000000L
//PCS_LANE4_COEFF2
#define PCS_LANE4_COEFF2__TxCoefficientPreCursor_lane4_gen2__SHIFT                                            0x0
#define PCS_LANE4_COEFF2__TxCoefficientMainCursor_lane4_gen2__SHIFT                                           0x8
#define PCS_LANE4_COEFF2__TxCoefficientPostCursor_lane4_gen2__SHIFT                                           0x10
#define PCS_LANE4_COEFF2__rxX_eq_ctle_boost_lane4_gen2__SHIFT                                                 0x18
#define PCS_LANE4_COEFF2__rxX_eq_ctle_pole_lane4_gen2__SHIFT                                                  0x1d
#define PCS_LANE4_COEFF2__TxCoefficientPreCursor_lane4_gen2_MASK                                              0x0000003FL
#define PCS_LANE4_COEFF2__TxCoefficientMainCursor_lane4_gen2_MASK                                             0x00003F00L
#define PCS_LANE4_COEFF2__TxCoefficientPostCursor_lane4_gen2_MASK                                             0x003F0000L
#define PCS_LANE4_COEFF2__rxX_eq_ctle_boost_lane4_gen2_MASK                                                   0x1F000000L
#define PCS_LANE4_COEFF2__rxX_eq_ctle_pole_lane4_gen2_MASK                                                    0xE0000000L
//PCS_LANE5_COEFF2
#define PCS_LANE5_COEFF2__TxCoefficientPreCursor_lane5_gen2__SHIFT                                            0x0
#define PCS_LANE5_COEFF2__TxCoefficientMainCursor_lane5_gen2__SHIFT                                           0x8
#define PCS_LANE5_COEFF2__TxCoefficientPostCursor_lane5_gen2__SHIFT                                           0x10
#define PCS_LANE5_COEFF2__rxX_eq_ctle_boost_lane5_gen2__SHIFT                                                 0x18
#define PCS_LANE5_COEFF2__rxX_eq_ctle_pole_lane5_gen2__SHIFT                                                  0x1d
#define PCS_LANE5_COEFF2__TxCoefficientPreCursor_lane5_gen2_MASK                                              0x0000003FL
#define PCS_LANE5_COEFF2__TxCoefficientMainCursor_lane5_gen2_MASK                                             0x00003F00L
#define PCS_LANE5_COEFF2__TxCoefficientPostCursor_lane5_gen2_MASK                                             0x003F0000L
#define PCS_LANE5_COEFF2__rxX_eq_ctle_boost_lane5_gen2_MASK                                                   0x1F000000L
#define PCS_LANE5_COEFF2__rxX_eq_ctle_pole_lane5_gen2_MASK                                                    0xE0000000L
//PCS_LANE6_COEFF2
#define PCS_LANE6_COEFF2__TxCoefficientPreCursor_lane6_gen2__SHIFT                                            0x0
#define PCS_LANE6_COEFF2__TxCoefficientMainCursor_lane6_gen2__SHIFT                                           0x8
#define PCS_LANE6_COEFF2__TxCoefficientPostCursor_lane6_gen2__SHIFT                                           0x10
#define PCS_LANE6_COEFF2__rxX_eq_ctle_boost_lane6_gen2__SHIFT                                                 0x18
#define PCS_LANE6_COEFF2__rxX_eq_ctle_pole_lane6_gen2__SHIFT                                                  0x1d
#define PCS_LANE6_COEFF2__TxCoefficientPreCursor_lane6_gen2_MASK                                              0x0000003FL
#define PCS_LANE6_COEFF2__TxCoefficientMainCursor_lane6_gen2_MASK                                             0x00003F00L
#define PCS_LANE6_COEFF2__TxCoefficientPostCursor_lane6_gen2_MASK                                             0x003F0000L
#define PCS_LANE6_COEFF2__rxX_eq_ctle_boost_lane6_gen2_MASK                                                   0x1F000000L
#define PCS_LANE6_COEFF2__rxX_eq_ctle_pole_lane6_gen2_MASK                                                    0xE0000000L
//PCS_LANE7_COEFF2
#define PCS_LANE7_COEFF2__TxCoefficientPreCursor_lane7_gen2__SHIFT                                            0x0
#define PCS_LANE7_COEFF2__TxCoefficientMainCursor_lane7_gen2__SHIFT                                           0x8
#define PCS_LANE7_COEFF2__TxCoefficientPostCursor_lane7_gen2__SHIFT                                           0x10
#define PCS_LANE7_COEFF2__rxX_eq_ctle_boost_lane7_gen2__SHIFT                                                 0x18
#define PCS_LANE7_COEFF2__rxX_eq_ctle_pole_lane7_gen2__SHIFT                                                  0x1d
#define PCS_LANE7_COEFF2__TxCoefficientPreCursor_lane7_gen2_MASK                                              0x0000003FL
#define PCS_LANE7_COEFF2__TxCoefficientMainCursor_lane7_gen2_MASK                                             0x00003F00L
#define PCS_LANE7_COEFF2__TxCoefficientPostCursor_lane7_gen2_MASK                                             0x003F0000L
#define PCS_LANE7_COEFF2__rxX_eq_ctle_boost_lane7_gen2_MASK                                                   0x1F000000L
#define PCS_LANE7_COEFF2__rxX_eq_ctle_pole_lane7_gen2_MASK                                                    0xE0000000L
//PCS_LANE8_COEFF2
#define PCS_LANE8_COEFF2__TxCoefficientPreCursor_lane8_gen2__SHIFT                                            0x0
#define PCS_LANE8_COEFF2__TxCoefficientMainCursor_lane8_gen2__SHIFT                                           0x8
#define PCS_LANE8_COEFF2__TxCoefficientPostCursor_lane8_gen2__SHIFT                                           0x10
#define PCS_LANE8_COEFF2__rxX_eq_ctle_boost_lane8_gen2__SHIFT                                                 0x18
#define PCS_LANE8_COEFF2__rxX_eq_ctle_pole_lane8_gen2__SHIFT                                                  0x1d
#define PCS_LANE8_COEFF2__TxCoefficientPreCursor_lane8_gen2_MASK                                              0x0000003FL
#define PCS_LANE8_COEFF2__TxCoefficientMainCursor_lane8_gen2_MASK                                             0x00003F00L
#define PCS_LANE8_COEFF2__TxCoefficientPostCursor_lane8_gen2_MASK                                             0x003F0000L
#define PCS_LANE8_COEFF2__rxX_eq_ctle_boost_lane8_gen2_MASK                                                   0x1F000000L
#define PCS_LANE8_COEFF2__rxX_eq_ctle_pole_lane8_gen2_MASK                                                    0xE0000000L
//PCS_LANE9_COEFF2
#define PCS_LANE9_COEFF2__TxCoefficientPreCursor_lane9_gen2__SHIFT                                            0x0
#define PCS_LANE9_COEFF2__TxCoefficientMainCursor_lane9_gen2__SHIFT                                           0x8
#define PCS_LANE9_COEFF2__TxCoefficientPostCursor_lane9_gen2__SHIFT                                           0x10
#define PCS_LANE9_COEFF2__rxX_eq_ctle_boost_lane9_gen2__SHIFT                                                 0x18
#define PCS_LANE9_COEFF2__rxX_eq_ctle_pole_lane9_gen2__SHIFT                                                  0x1d
#define PCS_LANE9_COEFF2__TxCoefficientPreCursor_lane9_gen2_MASK                                              0x0000003FL
#define PCS_LANE9_COEFF2__TxCoefficientMainCursor_lane9_gen2_MASK                                             0x00003F00L
#define PCS_LANE9_COEFF2__TxCoefficientPostCursor_lane9_gen2_MASK                                             0x003F0000L
#define PCS_LANE9_COEFF2__rxX_eq_ctle_boost_lane9_gen2_MASK                                                   0x1F000000L
#define PCS_LANE9_COEFF2__rxX_eq_ctle_pole_lane9_gen2_MASK                                                    0xE0000000L
//PCS_LANE10_COEFF2
#define PCS_LANE10_COEFF2__TxCoefficientPreCursor_lane10_gen2__SHIFT                                          0x0
#define PCS_LANE10_COEFF2__TxCoefficientMainCursor_lane10_gen2__SHIFT                                         0x8
#define PCS_LANE10_COEFF2__TxCoefficientPostCursor_lane10_gen2__SHIFT                                         0x10
#define PCS_LANE10_COEFF2__rxX_eq_ctle_boost_lane10_gen2__SHIFT                                               0x18
#define PCS_LANE10_COEFF2__rxX_eq_ctle_pole_lane10_gen2__SHIFT                                                0x1d
#define PCS_LANE10_COEFF2__TxCoefficientPreCursor_lane10_gen2_MASK                                            0x0000003FL
#define PCS_LANE10_COEFF2__TxCoefficientMainCursor_lane10_gen2_MASK                                           0x00003F00L
#define PCS_LANE10_COEFF2__TxCoefficientPostCursor_lane10_gen2_MASK                                           0x003F0000L
#define PCS_LANE10_COEFF2__rxX_eq_ctle_boost_lane10_gen2_MASK                                                 0x1F000000L
#define PCS_LANE10_COEFF2__rxX_eq_ctle_pole_lane10_gen2_MASK                                                  0xE0000000L
//PCS_LANE11_COEFF2
#define PCS_LANE11_COEFF2__TxCoefficientPreCursor_lane11_gen2__SHIFT                                          0x0
#define PCS_LANE11_COEFF2__TxCoefficientMainCursor_lane11_gen2__SHIFT                                         0x8
#define PCS_LANE11_COEFF2__TxCoefficientPostCursor_lane11_gen2__SHIFT                                         0x10
#define PCS_LANE11_COEFF2__rxX_eq_ctle_boost_lane11_gen2__SHIFT                                               0x18
#define PCS_LANE11_COEFF2__rxX_eq_ctle_pole_lane11_gen2__SHIFT                                                0x1d
#define PCS_LANE11_COEFF2__TxCoefficientPreCursor_lane11_gen2_MASK                                            0x0000003FL
#define PCS_LANE11_COEFF2__TxCoefficientMainCursor_lane11_gen2_MASK                                           0x00003F00L
#define PCS_LANE11_COEFF2__TxCoefficientPostCursor_lane11_gen2_MASK                                           0x003F0000L
#define PCS_LANE11_COEFF2__rxX_eq_ctle_boost_lane11_gen2_MASK                                                 0x1F000000L
#define PCS_LANE11_COEFF2__rxX_eq_ctle_pole_lane11_gen2_MASK                                                  0xE0000000L
//PCS_LANE12_COEFF2
#define PCS_LANE12_COEFF2__TxCoefficientPreCursor_lane12_gen2__SHIFT                                          0x0
#define PCS_LANE12_COEFF2__TxCoefficientMainCursor_lane12_gen2__SHIFT                                         0x8
#define PCS_LANE12_COEFF2__TxCoefficientPostCursor_lane12_gen2__SHIFT                                         0x10
#define PCS_LANE12_COEFF2__rxX_eq_ctle_boost_lane12_gen2__SHIFT                                               0x18
#define PCS_LANE12_COEFF2__rxX_eq_ctle_pole_lane12_gen2__SHIFT                                                0x1d
#define PCS_LANE12_COEFF2__TxCoefficientPreCursor_lane12_gen2_MASK                                            0x0000003FL
#define PCS_LANE12_COEFF2__TxCoefficientMainCursor_lane12_gen2_MASK                                           0x00003F00L
#define PCS_LANE12_COEFF2__TxCoefficientPostCursor_lane12_gen2_MASK                                           0x003F0000L
#define PCS_LANE12_COEFF2__rxX_eq_ctle_boost_lane12_gen2_MASK                                                 0x1F000000L
#define PCS_LANE12_COEFF2__rxX_eq_ctle_pole_lane12_gen2_MASK                                                  0xE0000000L
//PCS_LANE13_COEFF2
#define PCS_LANE13_COEFF2__TxCoefficientPreCursor_lane13_gen2__SHIFT                                          0x0
#define PCS_LANE13_COEFF2__TxCoefficientMainCursor_lane13_gen2__SHIFT                                         0x8
#define PCS_LANE13_COEFF2__TxCoefficientPostCursor_lane13_gen2__SHIFT                                         0x10
#define PCS_LANE13_COEFF2__rxX_eq_ctle_boost_lane13_gen2__SHIFT                                               0x18
#define PCS_LANE13_COEFF2__rxX_eq_ctle_pole_lane13_gen2__SHIFT                                                0x1d
#define PCS_LANE13_COEFF2__TxCoefficientPreCursor_lane13_gen2_MASK                                            0x0000003FL
#define PCS_LANE13_COEFF2__TxCoefficientMainCursor_lane13_gen2_MASK                                           0x00003F00L
#define PCS_LANE13_COEFF2__TxCoefficientPostCursor_lane13_gen2_MASK                                           0x003F0000L
#define PCS_LANE13_COEFF2__rxX_eq_ctle_boost_lane13_gen2_MASK                                                 0x1F000000L
#define PCS_LANE13_COEFF2__rxX_eq_ctle_pole_lane13_gen2_MASK                                                  0xE0000000L
//PCS_LANE14_COEFF2
#define PCS_LANE14_COEFF2__TxCoefficientPreCursor_lane14_gen2__SHIFT                                          0x0
#define PCS_LANE14_COEFF2__TxCoefficientMainCursor_lane14_gen2__SHIFT                                         0x8
#define PCS_LANE14_COEFF2__TxCoefficientPostCursor_lane14_gen2__SHIFT                                         0x10
#define PCS_LANE14_COEFF2__rxX_eq_ctle_boost_lane14_gen2__SHIFT                                               0x18
#define PCS_LANE14_COEFF2__rxX_eq_ctle_pole_lane14_gen2__SHIFT                                                0x1d
#define PCS_LANE14_COEFF2__TxCoefficientPreCursor_lane14_gen2_MASK                                            0x0000003FL
#define PCS_LANE14_COEFF2__TxCoefficientMainCursor_lane14_gen2_MASK                                           0x00003F00L
#define PCS_LANE14_COEFF2__TxCoefficientPostCursor_lane14_gen2_MASK                                           0x003F0000L
#define PCS_LANE14_COEFF2__rxX_eq_ctle_boost_lane14_gen2_MASK                                                 0x1F000000L
#define PCS_LANE14_COEFF2__rxX_eq_ctle_pole_lane14_gen2_MASK                                                  0xE0000000L
//PCS_LANE15_COEFF2
#define PCS_LANE15_COEFF2__TxCoefficientPreCursor_lane15_gen2__SHIFT                                          0x0
#define PCS_LANE15_COEFF2__TxCoefficientMainCursor_lane15_gen2__SHIFT                                         0x8
#define PCS_LANE15_COEFF2__TxCoefficientPostCursor_lane15_gen2__SHIFT                                         0x10
#define PCS_LANE15_COEFF2__rxX_eq_ctle_boost_lane15_gen2__SHIFT                                               0x18
#define PCS_LANE15_COEFF2__rxX_eq_ctle_pole_lane15_gen2__SHIFT                                                0x1d
#define PCS_LANE15_COEFF2__TxCoefficientPreCursor_lane15_gen2_MASK                                            0x0000003FL
#define PCS_LANE15_COEFF2__TxCoefficientMainCursor_lane15_gen2_MASK                                           0x00003F00L
#define PCS_LANE15_COEFF2__TxCoefficientPostCursor_lane15_gen2_MASK                                           0x003F0000L
#define PCS_LANE15_COEFF2__rxX_eq_ctle_boost_lane15_gen2_MASK                                                 0x1F000000L
#define PCS_LANE15_COEFF2__rxX_eq_ctle_pole_lane15_gen2_MASK                                                  0xE0000000L
//PCS_LANE0_COEFF3
#define PCS_LANE0_COEFF3__TxCoefficientPreCursor_lane0_gen3__SHIFT                                            0x0
#define PCS_LANE0_COEFF3__TxCoefficientMainCursor_lane0_gen3__SHIFT                                           0x8
#define PCS_LANE0_COEFF3__TxCoefficientPostCursor_lane0_gen3__SHIFT                                           0x10
#define PCS_LANE0_COEFF3__rxX_eq_ctle_boost_lane0_gen3__SHIFT                                                 0x18
#define PCS_LANE0_COEFF3__rxX_eq_ctle_pole_lane0_gen3__SHIFT                                                  0x1d
#define PCS_LANE0_COEFF3__TxCoefficientPreCursor_lane0_gen3_MASK                                              0x0000003FL
#define PCS_LANE0_COEFF3__TxCoefficientMainCursor_lane0_gen3_MASK                                             0x00003F00L
#define PCS_LANE0_COEFF3__TxCoefficientPostCursor_lane0_gen3_MASK                                             0x003F0000L
#define PCS_LANE0_COEFF3__rxX_eq_ctle_boost_lane0_gen3_MASK                                                   0x1F000000L
#define PCS_LANE0_COEFF3__rxX_eq_ctle_pole_lane0_gen3_MASK                                                    0xE0000000L
//PCS_LANE1_COEFF3
#define PCS_LANE1_COEFF3__TxCoefficientPreCursor_lane1_gen3__SHIFT                                            0x0
#define PCS_LANE1_COEFF3__TxCoefficientMainCursor_lane1_gen3__SHIFT                                           0x8
#define PCS_LANE1_COEFF3__TxCoefficientPostCursor_lane1_gen3__SHIFT                                           0x10
#define PCS_LANE1_COEFF3__rxX_eq_ctle_boost_lane1_gen3__SHIFT                                                 0x18
#define PCS_LANE1_COEFF3__rxX_eq_ctle_pole_lane1_gen3__SHIFT                                                  0x1d
#define PCS_LANE1_COEFF3__TxCoefficientPreCursor_lane1_gen3_MASK                                              0x0000003FL
#define PCS_LANE1_COEFF3__TxCoefficientMainCursor_lane1_gen3_MASK                                             0x00003F00L
#define PCS_LANE1_COEFF3__TxCoefficientPostCursor_lane1_gen3_MASK                                             0x003F0000L
#define PCS_LANE1_COEFF3__rxX_eq_ctle_boost_lane1_gen3_MASK                                                   0x1F000000L
#define PCS_LANE1_COEFF3__rxX_eq_ctle_pole_lane1_gen3_MASK                                                    0xE0000000L
//PCS_LANE2_COEFF3
#define PCS_LANE2_COEFF3__TxCoefficientPreCursor_lane2_gen3__SHIFT                                            0x0
#define PCS_LANE2_COEFF3__TxCoefficientMainCursor_lane2_gen3__SHIFT                                           0x8
#define PCS_LANE2_COEFF3__TxCoefficientPostCursor_lane2_gen3__SHIFT                                           0x10
#define PCS_LANE2_COEFF3__rxX_eq_ctle_boost_lane2_gen3__SHIFT                                                 0x18
#define PCS_LANE2_COEFF3__rxX_eq_ctle_pole_lane2_gen3__SHIFT                                                  0x1d
#define PCS_LANE2_COEFF3__TxCoefficientPreCursor_lane2_gen3_MASK                                              0x0000003FL
#define PCS_LANE2_COEFF3__TxCoefficientMainCursor_lane2_gen3_MASK                                             0x00003F00L
#define PCS_LANE2_COEFF3__TxCoefficientPostCursor_lane2_gen3_MASK                                             0x003F0000L
#define PCS_LANE2_COEFF3__rxX_eq_ctle_boost_lane2_gen3_MASK                                                   0x1F000000L
#define PCS_LANE2_COEFF3__rxX_eq_ctle_pole_lane2_gen3_MASK                                                    0xE0000000L
//PCS_LANE3_COEFF3
#define PCS_LANE3_COEFF3__TxCoefficientPreCursor_lane3_gen3__SHIFT                                            0x0
#define PCS_LANE3_COEFF3__TxCoefficientMainCursor_lane3_gen3__SHIFT                                           0x8
#define PCS_LANE3_COEFF3__TxCoefficientPostCursor_lane3_gen3__SHIFT                                           0x10
#define PCS_LANE3_COEFF3__rxX_eq_ctle_boost_lane3_gen3__SHIFT                                                 0x18
#define PCS_LANE3_COEFF3__rxX_eq_ctle_pole_lane3_gen3__SHIFT                                                  0x1d
#define PCS_LANE3_COEFF3__TxCoefficientPreCursor_lane3_gen3_MASK                                              0x0000003FL
#define PCS_LANE3_COEFF3__TxCoefficientMainCursor_lane3_gen3_MASK                                             0x00003F00L
#define PCS_LANE3_COEFF3__TxCoefficientPostCursor_lane3_gen3_MASK                                             0x003F0000L
#define PCS_LANE3_COEFF3__rxX_eq_ctle_boost_lane3_gen3_MASK                                                   0x1F000000L
#define PCS_LANE3_COEFF3__rxX_eq_ctle_pole_lane3_gen3_MASK                                                    0xE0000000L
//PCS_LANE4_COEFF3
#define PCS_LANE4_COEFF3__TxCoefficientPreCursor_lane4_gen3__SHIFT                                            0x0
#define PCS_LANE4_COEFF3__TxCoefficientMainCursor_lane4_gen3__SHIFT                                           0x8
#define PCS_LANE4_COEFF3__TxCoefficientPostCursor_lane4_gen3__SHIFT                                           0x10
#define PCS_LANE4_COEFF3__rxX_eq_ctle_boost_lane4_gen3__SHIFT                                                 0x18
#define PCS_LANE4_COEFF3__rxX_eq_ctle_pole_lane4_gen3__SHIFT                                                  0x1d
#define PCS_LANE4_COEFF3__TxCoefficientPreCursor_lane4_gen3_MASK                                              0x0000003FL
#define PCS_LANE4_COEFF3__TxCoefficientMainCursor_lane4_gen3_MASK                                             0x00003F00L
#define PCS_LANE4_COEFF3__TxCoefficientPostCursor_lane4_gen3_MASK                                             0x003F0000L
#define PCS_LANE4_COEFF3__rxX_eq_ctle_boost_lane4_gen3_MASK                                                   0x1F000000L
#define PCS_LANE4_COEFF3__rxX_eq_ctle_pole_lane4_gen3_MASK                                                    0xE0000000L
//PCS_LANE5_COEFF3
#define PCS_LANE5_COEFF3__TxCoefficientPreCursor_lane5_gen3__SHIFT                                            0x0
#define PCS_LANE5_COEFF3__TxCoefficientMainCursor_lane5_gen3__SHIFT                                           0x8
#define PCS_LANE5_COEFF3__TxCoefficientPostCursor_lane5_gen3__SHIFT                                           0x10
#define PCS_LANE5_COEFF3__rxX_eq_ctle_boost_lane5_gen3__SHIFT                                                 0x18
#define PCS_LANE5_COEFF3__rxX_eq_ctle_pole_lane5_gen3__SHIFT                                                  0x1d
#define PCS_LANE5_COEFF3__TxCoefficientPreCursor_lane5_gen3_MASK                                              0x0000003FL
#define PCS_LANE5_COEFF3__TxCoefficientMainCursor_lane5_gen3_MASK                                             0x00003F00L
#define PCS_LANE5_COEFF3__TxCoefficientPostCursor_lane5_gen3_MASK                                             0x003F0000L
#define PCS_LANE5_COEFF3__rxX_eq_ctle_boost_lane5_gen3_MASK                                                   0x1F000000L
#define PCS_LANE5_COEFF3__rxX_eq_ctle_pole_lane5_gen3_MASK                                                    0xE0000000L
//PCS_LANE6_COEFF3
#define PCS_LANE6_COEFF3__TxCoefficientPreCursor_lane6_gen3__SHIFT                                            0x0
#define PCS_LANE6_COEFF3__TxCoefficientMainCursor_lane6_gen3__SHIFT                                           0x8
#define PCS_LANE6_COEFF3__TxCoefficientPostCursor_lane6_gen3__SHIFT                                           0x10
#define PCS_LANE6_COEFF3__rxX_eq_ctle_boost_lane6_gen3__SHIFT                                                 0x18
#define PCS_LANE6_COEFF3__rxX_eq_ctle_pole_lane6_gen3__SHIFT                                                  0x1d
#define PCS_LANE6_COEFF3__TxCoefficientPreCursor_lane6_gen3_MASK                                              0x0000003FL
#define PCS_LANE6_COEFF3__TxCoefficientMainCursor_lane6_gen3_MASK                                             0x00003F00L
#define PCS_LANE6_COEFF3__TxCoefficientPostCursor_lane6_gen3_MASK                                             0x003F0000L
#define PCS_LANE6_COEFF3__rxX_eq_ctle_boost_lane6_gen3_MASK                                                   0x1F000000L
#define PCS_LANE6_COEFF3__rxX_eq_ctle_pole_lane6_gen3_MASK                                                    0xE0000000L
//PCS_LANE7_COEFF3
#define PCS_LANE7_COEFF3__TxCoefficientPreCursor_lane7_gen3__SHIFT                                            0x0
#define PCS_LANE7_COEFF3__TxCoefficientMainCursor_lane7_gen3__SHIFT                                           0x8
#define PCS_LANE7_COEFF3__TxCoefficientPostCursor_lane7_gen3__SHIFT                                           0x10
#define PCS_LANE7_COEFF3__rxX_eq_ctle_boost_lane7_gen3__SHIFT                                                 0x18
#define PCS_LANE7_COEFF3__rxX_eq_ctle_pole_lane7_gen3__SHIFT                                                  0x1d
#define PCS_LANE7_COEFF3__TxCoefficientPreCursor_lane7_gen3_MASK                                              0x0000003FL
#define PCS_LANE7_COEFF3__TxCoefficientMainCursor_lane7_gen3_MASK                                             0x00003F00L
#define PCS_LANE7_COEFF3__TxCoefficientPostCursor_lane7_gen3_MASK                                             0x003F0000L
#define PCS_LANE7_COEFF3__rxX_eq_ctle_boost_lane7_gen3_MASK                                                   0x1F000000L
#define PCS_LANE7_COEFF3__rxX_eq_ctle_pole_lane7_gen3_MASK                                                    0xE0000000L
//PCS_LANE8_COEFF3
#define PCS_LANE8_COEFF3__TxCoefficientPreCursor_lane8_gen3__SHIFT                                            0x0
#define PCS_LANE8_COEFF3__TxCoefficientMainCursor_lane8_gen3__SHIFT                                           0x8
#define PCS_LANE8_COEFF3__TxCoefficientPostCursor_lane8_gen3__SHIFT                                           0x10
#define PCS_LANE8_COEFF3__rxX_eq_ctle_boost_lane8_gen3__SHIFT                                                 0x18
#define PCS_LANE8_COEFF3__rxX_eq_ctle_pole_lane8_gen3__SHIFT                                                  0x1d
#define PCS_LANE8_COEFF3__TxCoefficientPreCursor_lane8_gen3_MASK                                              0x0000003FL
#define PCS_LANE8_COEFF3__TxCoefficientMainCursor_lane8_gen3_MASK                                             0x00003F00L
#define PCS_LANE8_COEFF3__TxCoefficientPostCursor_lane8_gen3_MASK                                             0x003F0000L
#define PCS_LANE8_COEFF3__rxX_eq_ctle_boost_lane8_gen3_MASK                                                   0x1F000000L
#define PCS_LANE8_COEFF3__rxX_eq_ctle_pole_lane8_gen3_MASK                                                    0xE0000000L
//PCS_LANE9_COEFF3
#define PCS_LANE9_COEFF3__TxCoefficientPreCursor_lane9_gen3__SHIFT                                            0x0
#define PCS_LANE9_COEFF3__TxCoefficientMainCursor_lane9_gen3__SHIFT                                           0x8
#define PCS_LANE9_COEFF3__TxCoefficientPostCursor_lane9_gen3__SHIFT                                           0x10
#define PCS_LANE9_COEFF3__rxX_eq_ctle_boost_lane9_gen3__SHIFT                                                 0x18
#define PCS_LANE9_COEFF3__rxX_eq_ctle_pole_lane9_gen3__SHIFT                                                  0x1d
#define PCS_LANE9_COEFF3__TxCoefficientPreCursor_lane9_gen3_MASK                                              0x0000003FL
#define PCS_LANE9_COEFF3__TxCoefficientMainCursor_lane9_gen3_MASK                                             0x00003F00L
#define PCS_LANE9_COEFF3__TxCoefficientPostCursor_lane9_gen3_MASK                                             0x003F0000L
#define PCS_LANE9_COEFF3__rxX_eq_ctle_boost_lane9_gen3_MASK                                                   0x1F000000L
#define PCS_LANE9_COEFF3__rxX_eq_ctle_pole_lane9_gen3_MASK                                                    0xE0000000L
//PCS_LANE10_COEFF3
#define PCS_LANE10_COEFF3__TxCoefficientPreCursor_lane10_gen3__SHIFT                                          0x0
#define PCS_LANE10_COEFF3__TxCoefficientMainCursor_lane10_gen3__SHIFT                                         0x8
#define PCS_LANE10_COEFF3__TxCoefficientPostCursor_lane10_gen3__SHIFT                                         0x10
#define PCS_LANE10_COEFF3__rxX_eq_ctle_boost_lane10_gen3__SHIFT                                               0x18
#define PCS_LANE10_COEFF3__rxX_eq_ctle_pole_lane10_gen3__SHIFT                                                0x1d
#define PCS_LANE10_COEFF3__TxCoefficientPreCursor_lane10_gen3_MASK                                            0x0000003FL
#define PCS_LANE10_COEFF3__TxCoefficientMainCursor_lane10_gen3_MASK                                           0x00003F00L
#define PCS_LANE10_COEFF3__TxCoefficientPostCursor_lane10_gen3_MASK                                           0x003F0000L
#define PCS_LANE10_COEFF3__rxX_eq_ctle_boost_lane10_gen3_MASK                                                 0x1F000000L
#define PCS_LANE10_COEFF3__rxX_eq_ctle_pole_lane10_gen3_MASK                                                  0xE0000000L
//PCS_LANE11_COEFF3
#define PCS_LANE11_COEFF3__TxCoefficientPreCursor_lane11_gen3__SHIFT                                          0x0
#define PCS_LANE11_COEFF3__TxCoefficientMainCursor_lane11_gen3__SHIFT                                         0x8
#define PCS_LANE11_COEFF3__TxCoefficientPostCursor_lane11_gen3__SHIFT                                         0x10
#define PCS_LANE11_COEFF3__rxX_eq_ctle_boost_lane11_gen3__SHIFT                                               0x18
#define PCS_LANE11_COEFF3__rxX_eq_ctle_pole_lane11_gen3__SHIFT                                                0x1d
#define PCS_LANE11_COEFF3__TxCoefficientPreCursor_lane11_gen3_MASK                                            0x0000003FL
#define PCS_LANE11_COEFF3__TxCoefficientMainCursor_lane11_gen3_MASK                                           0x00003F00L
#define PCS_LANE11_COEFF3__TxCoefficientPostCursor_lane11_gen3_MASK                                           0x003F0000L
#define PCS_LANE11_COEFF3__rxX_eq_ctle_boost_lane11_gen3_MASK                                                 0x1F000000L
#define PCS_LANE11_COEFF3__rxX_eq_ctle_pole_lane11_gen3_MASK                                                  0xE0000000L
//PCS_LANE12_COEFF3
#define PCS_LANE12_COEFF3__TxCoefficientPreCursor_lane12_gen3__SHIFT                                          0x0
#define PCS_LANE12_COEFF3__TxCoefficientMainCursor_lane12_gen3__SHIFT                                         0x8
#define PCS_LANE12_COEFF3__TxCoefficientPostCursor_lane12_gen3__SHIFT                                         0x10
#define PCS_LANE12_COEFF3__rxX_eq_ctle_boost_lane12_gen3__SHIFT                                               0x18
#define PCS_LANE12_COEFF3__rxX_eq_ctle_pole_lane12_gen3__SHIFT                                                0x1d
#define PCS_LANE12_COEFF3__TxCoefficientPreCursor_lane12_gen3_MASK                                            0x0000003FL
#define PCS_LANE12_COEFF3__TxCoefficientMainCursor_lane12_gen3_MASK                                           0x00003F00L
#define PCS_LANE12_COEFF3__TxCoefficientPostCursor_lane12_gen3_MASK                                           0x003F0000L
#define PCS_LANE12_COEFF3__rxX_eq_ctle_boost_lane12_gen3_MASK                                                 0x1F000000L
#define PCS_LANE12_COEFF3__rxX_eq_ctle_pole_lane12_gen3_MASK                                                  0xE0000000L
//PCS_LANE13_COEFF3
#define PCS_LANE13_COEFF3__TxCoefficientPreCursor_lane13_gen3__SHIFT                                          0x0
#define PCS_LANE13_COEFF3__TxCoefficientMainCursor_lane13_gen3__SHIFT                                         0x8
#define PCS_LANE13_COEFF3__TxCoefficientPostCursor_lane13_gen3__SHIFT                                         0x10
#define PCS_LANE13_COEFF3__rxX_eq_ctle_boost_lane13_gen3__SHIFT                                               0x18
#define PCS_LANE13_COEFF3__rxX_eq_ctle_pole_lane13_gen3__SHIFT                                                0x1d
#define PCS_LANE13_COEFF3__TxCoefficientPreCursor_lane13_gen3_MASK                                            0x0000003FL
#define PCS_LANE13_COEFF3__TxCoefficientMainCursor_lane13_gen3_MASK                                           0x00003F00L
#define PCS_LANE13_COEFF3__TxCoefficientPostCursor_lane13_gen3_MASK                                           0x003F0000L
#define PCS_LANE13_COEFF3__rxX_eq_ctle_boost_lane13_gen3_MASK                                                 0x1F000000L
#define PCS_LANE13_COEFF3__rxX_eq_ctle_pole_lane13_gen3_MASK                                                  0xE0000000L
//PCS_LANE14_COEFF3
#define PCS_LANE14_COEFF3__TxCoefficientPreCursor_lane14_gen3__SHIFT                                          0x0
#define PCS_LANE14_COEFF3__TxCoefficientMainCursor_lane14_gen3__SHIFT                                         0x8
#define PCS_LANE14_COEFF3__TxCoefficientPostCursor_lane14_gen3__SHIFT                                         0x10
#define PCS_LANE14_COEFF3__rxX_eq_ctle_boost_lane14_gen3__SHIFT                                               0x18
#define PCS_LANE14_COEFF3__rxX_eq_ctle_pole_lane14_gen3__SHIFT                                                0x1d
#define PCS_LANE14_COEFF3__TxCoefficientPreCursor_lane14_gen3_MASK                                            0x0000003FL
#define PCS_LANE14_COEFF3__TxCoefficientMainCursor_lane14_gen3_MASK                                           0x00003F00L
#define PCS_LANE14_COEFF3__TxCoefficientPostCursor_lane14_gen3_MASK                                           0x003F0000L
#define PCS_LANE14_COEFF3__rxX_eq_ctle_boost_lane14_gen3_MASK                                                 0x1F000000L
#define PCS_LANE14_COEFF3__rxX_eq_ctle_pole_lane14_gen3_MASK                                                  0xE0000000L
//PCS_LANE15_COEFF3
#define PCS_LANE15_COEFF3__TxCoefficientPreCursor_lane15_gen3__SHIFT                                          0x0
#define PCS_LANE15_COEFF3__TxCoefficientMainCursor_lane15_gen3__SHIFT                                         0x8
#define PCS_LANE15_COEFF3__TxCoefficientPostCursor_lane15_gen3__SHIFT                                         0x10
#define PCS_LANE15_COEFF3__rxX_eq_ctle_boost_lane15_gen3__SHIFT                                               0x18
#define PCS_LANE15_COEFF3__rxX_eq_ctle_pole_lane15_gen3__SHIFT                                                0x1d
#define PCS_LANE15_COEFF3__TxCoefficientPreCursor_lane15_gen3_MASK                                            0x0000003FL
#define PCS_LANE15_COEFF3__TxCoefficientMainCursor_lane15_gen3_MASK                                           0x00003F00L
#define PCS_LANE15_COEFF3__TxCoefficientPostCursor_lane15_gen3_MASK                                           0x003F0000L
#define PCS_LANE15_COEFF3__rxX_eq_ctle_boost_lane15_gen3_MASK                                                 0x1F000000L
#define PCS_LANE15_COEFF3__rxX_eq_ctle_pole_lane15_gen3_MASK                                                  0xE0000000L


// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns1_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_LO__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_IDCODE_HI__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                   0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                         0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                        0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                        0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                      0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                     0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                      0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                 0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                            0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__BG_EN__SHIFT                                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                              0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK                                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK                                            0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK                                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK                                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ASIC_IN__BG_EN_MASK                                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                      0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                              0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                  0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                 0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                               0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                             0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK                                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                         0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                      0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                             0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK                                          0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__bypass_bg__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__vref_sel_fastreg__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__chop_en__SHIFT                                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__NC74__SHIFT                                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__RESERVED_15_8__SHIFT                                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__bypass_bg_MASK                                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__vref_sel_fastreg_MASK                                            0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__chop_en_MASK                                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__NC74_MASK                                                        0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_ANA_BG__RESERVED_15_8_MASK                                               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                    0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__STAT_MASK                                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                           0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                      0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                    0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                 0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                          0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_LO__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_IDCODE_HI__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                  0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                        0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                       0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                       0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                     0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                     0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                  0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__BG_EN__SHIFT                                               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                             0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK                                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK                                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK                                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK                                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ASIC_IN__BG_EN_MASK                                                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                     0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                     0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                       0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                 0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK                                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                        0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                     0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                            0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK                                         0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__bypass_bg__SHIFT                                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__vref_sel_fastreg__SHIFT                                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__chop_en__SHIFT                                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__NC74__SHIFT                                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__RESERVED_15_8__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__bypass_bg_MASK                                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__vref_sel_fastreg_MASK                                           0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__chop_en_MASK                                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__NC74_MASK                                                       0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_ANA_BG__RESERVED_15_8_MASK                                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__STAT_MASK                                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                          0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                     0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                         0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                   0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK                                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL


// addressBlock: nbio_lcu_kpfifo_kpfifo1_kpfifo_dir
//KPFIFO1_PRI_TX_FIFO_HSCID
#define KPFIFO1_PRI_TX_FIFO_HSCID__HwRev__SHIFT                                                               0x0
#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT                                                            0x6
#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT                                                            0xd
#define KPFIFO1_PRI_TX_FIFO_HSCID__HwRev_MASK                                                                 0x0000003FL
#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMinVer_MASK                                                              0x00001FC0L
#define KPFIFO1_PRI_TX_FIFO_HSCID__HwMajVer_MASK                                                              0x000FE000L
//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT                                                     0x0
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT                                                  0x10
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT                                                 0x1a
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK                                                       0x000000FFL
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK                                                   0x04000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK                                                     0x80000000L
//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT                                                     0x0
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT                                                  0x10
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT                                                 0x1a
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK                                                       0x000000FFL
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK                                                   0x04000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK                                                     0x80000000L
//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT                                                     0x0
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT                                                  0x10
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT                                                 0x1a
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK                                                       0x000000FFL
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK                                                   0x04000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK                                                     0x80000000L
//KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT                                                     0x0
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT                                                  0x10
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT                                                 0x1a
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK                                                       0x000000FFL
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK                                                   0x04000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO1_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK                                                     0x80000000L
//KPFIFO1_PCS_PMA_SOFT_RESET
#define KPFIFO1_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT                                           0x0
#define KPFIFO1_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK                                             0x00000001L


// addressBlock: nbio_lcu_kpnp_kpnp1_kpnp_dir
//KPNP_SNPS1_KPNP_HWSCVER
#define KPNP_SNPS1_KPNP_HWSCVER__hw_revision__SHIFT                                                           0x0
#define KPNP_SNPS1_KPNP_HWSCVER__hw_minor_version_number__SHIFT                                               0x6
#define KPNP_SNPS1_KPNP_HWSCVER__hw_major_version_number__SHIFT                                               0xd
#define KPNP_SNPS1_KPNP_HWSCVER__hw_revision_MASK                                                             0x0000003FL
#define KPNP_SNPS1_KPNP_HWSCVER__hw_minor_version_number_MASK                                                 0x00001FC0L
#define KPNP_SNPS1_KPNP_HWSCVER__hw_major_version_number_MASK                                                 0x000FE000L
//KPNP_SNPS1_KPNP_PHY_INFO
#define KPNP_SNPS1_KPNP_PHY_INFO__HwRev__SHIFT                                                                0x0
#define KPNP_SNPS1_KPNP_PHY_INFO__PHYVer__SHIFT                                                               0x6
#define KPNP_SNPS1_KPNP_PHY_INFO__Technology__SHIFT                                                           0xd
#define KPNP_SNPS1_KPNP_PHY_INFO__Type__SHIFT                                                                 0x14
#define KPNP_SNPS1_KPNP_PHY_INFO__VendorID__SHIFT                                                             0x1a
#define KPNP_SNPS1_KPNP_PHY_INFO__HwRev_MASK                                                                  0x0000003FL
#define KPNP_SNPS1_KPNP_PHY_INFO__PHYVer_MASK                                                                 0x00001FC0L
#define KPNP_SNPS1_KPNP_PHY_INFO__Technology_MASK                                                             0x000FE000L
#define KPNP_SNPS1_KPNP_PHY_INFO__Type_MASK                                                                   0x03F00000L
#define KPNP_SNPS1_KPNP_PHY_INFO__VendorID_MASK                                                               0xFC000000L
//KPNP_SNPS1_KPNP_LANE_ID
#define KPNP_SNPS1_KPNP_LANE_ID__NodeStartLane__SHIFT                                                         0x0
#define KPNP_SNPS1_KPNP_LANE_ID__NodeEndLane__SHIFT                                                           0x8
#define KPNP_SNPS1_KPNP_LANE_ID__NodeStartLane_MASK                                                           0x000000FFL
#define KPNP_SNPS1_KPNP_LANE_ID__NodeEndLane_MASK                                                             0x0000FF00L
//KPNP_SNPS1_KPNP_LANE_REQ_CONTROL
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT                                                     0x0
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT                                                     0x1
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT                                                     0x2
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT                                                     0x3
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT                                                     0x4
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT                                                     0x5
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT                                                     0x6
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT                                                     0x7
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK                                                       0x00000001L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK                                                       0x00000002L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK                                                       0x00000004L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK                                                       0x00000008L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK                                                       0x00000010L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK                                                       0x00000020L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK                                                       0x00000040L
#define KPNP_SNPS1_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK                                                       0x00000080L
//KPNP_SNPS1_KPNP_LANE_REQ_STATUS
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT                                                      0x0
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT                                                      0x1
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT                                                      0x2
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT                                                      0x3
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT                                                      0x4
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT                                                      0x5
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT                                                      0x6
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT                                                      0x7
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK                                                        0x00000001L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK                                                        0x00000002L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK                                                        0x00000004L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK                                                        0x00000008L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK                                                        0x00000010L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK                                                        0x00000020L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK                                                        0x00000040L
#define KPNP_SNPS1_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK                                                        0x00000080L
//KPNP_SNPS1_KPNP_PMA_CONTROL0
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT                                                      0x0
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT                                                   0x10
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT                                                   0x11
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT                                                   0x12
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT                                                   0x13
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT                                                   0x14
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT                                                   0x15
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT                                                   0x16
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT                                                   0x17
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__ref_use_pad_MASK                                                        0x00000001L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK                                                     0x00010000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK                                                     0x00020000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK                                                     0x00040000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK                                                     0x00080000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK                                                     0x00100000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK                                                     0x00200000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK                                                     0x00400000L
#define KPNP_SNPS1_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK                                                     0x00800000L
//KPNP_SNPS1_KPNP_PMA_CONTROL1
#define KPNP_SNPS1_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT                                                     0x0
#define KPNP_SNPS1_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT                                                    0x5
#define KPNP_SNPS1_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK                                                       0x0000001FL
#define KPNP_SNPS1_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK                                                      0x000000E0L
//KPNP_SNPS1_KPNP_PMA_CONTROL2
#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT                                               0x0
#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT                                                  0x1
#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT                                       0x2
#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Disable_MASK                                                 0x00000001L
#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Mode_MASK                                                    0x00000002L
#define KPNP_SNPS1_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK                                         0x0000001CL
//KPNP_SNPS1_KPNP_PHY_SOFT_RESET
#define KPNP_SNPS1_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT                                                 0x0
#define KPNP_SNPS1_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK                                                   0x00000001L
//KPNP_SNPS1_KPNP_LANE_SOFT_RESET
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT                                             0x0
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT                                             0x1
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT                                             0x2
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT                                             0x3
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT                                             0x4
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT                                             0x5
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT                                             0x6
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT                                             0x7
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK                                               0x00000001L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK                                               0x00000002L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK                                               0x00000004L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK                                               0x00000008L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK                                               0x00000010L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK                                               0x00000020L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK                                               0x00000040L
#define KPNP_SNPS1_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK                                               0x00000080L
//KPNP_SNPS1_REG_RST_CTRL
#define KPNP_SNPS1_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT                                          0x0
#define KPNP_SNPS1_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK                                            0x00000001L


// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns2_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_LO__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_IDCODE_HI__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                   0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                         0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                        0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                        0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                      0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                     0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                      0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                 0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                            0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__BG_EN__SHIFT                                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                              0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK                                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK                                            0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK                                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK                                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ASIC_IN__BG_EN_MASK                                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                      0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                              0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                  0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                 0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                               0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                             0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK                                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                         0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                      0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                             0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK                                          0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__bypass_bg__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__vref_sel_fastreg__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__chop_en__SHIFT                                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__NC74__SHIFT                                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__RESERVED_15_8__SHIFT                                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__bypass_bg_MASK                                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__vref_sel_fastreg_MASK                                            0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__chop_en_MASK                                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__NC74_MASK                                                        0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_ANA_BG__RESERVED_15_8_MASK                                               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                    0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__STAT_MASK                                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                           0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                      0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                    0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                 0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                          0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_LO__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_IDCODE_HI__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                  0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                        0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                       0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                       0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                     0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                     0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                  0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__BG_EN__SHIFT                                               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                             0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK                                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK                                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK                                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK                                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ASIC_IN__BG_EN_MASK                                                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                     0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                     0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                       0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                 0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK                                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                        0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                     0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                            0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK                                         0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__bypass_bg__SHIFT                                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__vref_sel_fastreg__SHIFT                                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__chop_en__SHIFT                                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__NC74__SHIFT                                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__RESERVED_15_8__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__bypass_bg_MASK                                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__vref_sel_fastreg_MASK                                           0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__chop_en_MASK                                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__NC74_MASK                                                       0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_ANA_BG__RESERVED_15_8_MASK                                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__STAT_MASK                                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                          0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                     0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                         0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                   0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK                                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL


// addressBlock: nbio_lcu_kpfifo_kpfifo2_kpfifo_dir
//KPFIFO2_PRI_TX_FIFO_HSCID
#define KPFIFO2_PRI_TX_FIFO_HSCID__HwRev__SHIFT                                                               0x0
#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT                                                            0x6
#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT                                                            0xd
#define KPFIFO2_PRI_TX_FIFO_HSCID__HwRev_MASK                                                                 0x0000003FL
#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMinVer_MASK                                                              0x00001FC0L
#define KPFIFO2_PRI_TX_FIFO_HSCID__HwMajVer_MASK                                                              0x000FE000L
//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT                                                     0x0
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT                                                  0x10
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT                                                 0x1a
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK                                                       0x000000FFL
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK                                                   0x04000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK                                                     0x80000000L
//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT                                                     0x0
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT                                                  0x10
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT                                                 0x1a
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK                                                       0x000000FFL
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK                                                   0x04000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK                                                     0x80000000L
//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT                                                     0x0
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT                                                  0x10
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT                                                 0x1a
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK                                                       0x000000FFL
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK                                                   0x04000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK                                                     0x80000000L
//KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT                                                     0x0
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT                                                  0x10
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT                                                 0x1a
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK                                                       0x000000FFL
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK                                                   0x04000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO2_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK                                                     0x80000000L
//KPFIFO2_PCS_PMA_SOFT_RESET
#define KPFIFO2_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT                                           0x0
#define KPFIFO2_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK                                             0x00000001L


// addressBlock: nbio_lcu_kpnp_kpnp2_kpnp_dir
//KPNP_SNPS2_KPNP_HWSCVER
#define KPNP_SNPS2_KPNP_HWSCVER__hw_revision__SHIFT                                                           0x0
#define KPNP_SNPS2_KPNP_HWSCVER__hw_minor_version_number__SHIFT                                               0x6
#define KPNP_SNPS2_KPNP_HWSCVER__hw_major_version_number__SHIFT                                               0xd
#define KPNP_SNPS2_KPNP_HWSCVER__hw_revision_MASK                                                             0x0000003FL
#define KPNP_SNPS2_KPNP_HWSCVER__hw_minor_version_number_MASK                                                 0x00001FC0L
#define KPNP_SNPS2_KPNP_HWSCVER__hw_major_version_number_MASK                                                 0x000FE000L
//KPNP_SNPS2_KPNP_PHY_INFO
#define KPNP_SNPS2_KPNP_PHY_INFO__HwRev__SHIFT                                                                0x0
#define KPNP_SNPS2_KPNP_PHY_INFO__PHYVer__SHIFT                                                               0x6
#define KPNP_SNPS2_KPNP_PHY_INFO__Technology__SHIFT                                                           0xd
#define KPNP_SNPS2_KPNP_PHY_INFO__Type__SHIFT                                                                 0x14
#define KPNP_SNPS2_KPNP_PHY_INFO__VendorID__SHIFT                                                             0x1a
#define KPNP_SNPS2_KPNP_PHY_INFO__HwRev_MASK                                                                  0x0000003FL
#define KPNP_SNPS2_KPNP_PHY_INFO__PHYVer_MASK                                                                 0x00001FC0L
#define KPNP_SNPS2_KPNP_PHY_INFO__Technology_MASK                                                             0x000FE000L
#define KPNP_SNPS2_KPNP_PHY_INFO__Type_MASK                                                                   0x03F00000L
#define KPNP_SNPS2_KPNP_PHY_INFO__VendorID_MASK                                                               0xFC000000L
//KPNP_SNPS2_KPNP_LANE_ID
#define KPNP_SNPS2_KPNP_LANE_ID__NodeStartLane__SHIFT                                                         0x0
#define KPNP_SNPS2_KPNP_LANE_ID__NodeEndLane__SHIFT                                                           0x8
#define KPNP_SNPS2_KPNP_LANE_ID__NodeStartLane_MASK                                                           0x000000FFL
#define KPNP_SNPS2_KPNP_LANE_ID__NodeEndLane_MASK                                                             0x0000FF00L
//KPNP_SNPS2_KPNP_LANE_REQ_CONTROL
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT                                                     0x0
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT                                                     0x1
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT                                                     0x2
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT                                                     0x3
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT                                                     0x4
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT                                                     0x5
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT                                                     0x6
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT                                                     0x7
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK                                                       0x00000001L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK                                                       0x00000002L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK                                                       0x00000004L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK                                                       0x00000008L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK                                                       0x00000010L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK                                                       0x00000020L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK                                                       0x00000040L
#define KPNP_SNPS2_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK                                                       0x00000080L
//KPNP_SNPS2_KPNP_LANE_REQ_STATUS
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT                                                      0x0
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT                                                      0x1
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT                                                      0x2
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT                                                      0x3
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT                                                      0x4
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT                                                      0x5
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT                                                      0x6
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT                                                      0x7
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK                                                        0x00000001L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK                                                        0x00000002L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK                                                        0x00000004L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK                                                        0x00000008L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK                                                        0x00000010L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK                                                        0x00000020L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK                                                        0x00000040L
#define KPNP_SNPS2_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK                                                        0x00000080L
//KPNP_SNPS2_KPNP_PMA_CONTROL0
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT                                                      0x0
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT                                                   0x10
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT                                                   0x11
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT                                                   0x12
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT                                                   0x13
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT                                                   0x14
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT                                                   0x15
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT                                                   0x16
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT                                                   0x17
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__ref_use_pad_MASK                                                        0x00000001L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK                                                     0x00010000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK                                                     0x00020000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK                                                     0x00040000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK                                                     0x00080000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK                                                     0x00100000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK                                                     0x00200000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK                                                     0x00400000L
#define KPNP_SNPS2_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK                                                     0x00800000L
//KPNP_SNPS2_KPNP_PMA_CONTROL1
#define KPNP_SNPS2_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT                                                     0x0
#define KPNP_SNPS2_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT                                                    0x5
#define KPNP_SNPS2_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK                                                       0x0000001FL
#define KPNP_SNPS2_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK                                                      0x000000E0L
//KPNP_SNPS2_KPNP_PMA_CONTROL2
#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT                                               0x0
#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT                                                  0x1
#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT                                       0x2
#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Disable_MASK                                                 0x00000001L
#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Mode_MASK                                                    0x00000002L
#define KPNP_SNPS2_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK                                         0x0000001CL
//KPNP_SNPS2_KPNP_PHY_SOFT_RESET
#define KPNP_SNPS2_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT                                                 0x0
#define KPNP_SNPS2_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK                                                   0x00000001L
//KPNP_SNPS2_KPNP_LANE_SOFT_RESET
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT                                             0x0
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT                                             0x1
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT                                             0x2
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT                                             0x3
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT                                             0x4
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT                                             0x5
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT                                             0x6
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT                                             0x7
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK                                               0x00000001L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK                                               0x00000002L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK                                               0x00000004L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK                                               0x00000008L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK                                               0x00000010L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK                                               0x00000020L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK                                               0x00000040L
#define KPNP_SNPS2_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK                                               0x00000080L
//KPNP_SNPS2_REG_RST_CTRL
#define KPNP_SNPS2_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT                                          0x0
#define KPNP_SNPS2_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK                                            0x00000001L


// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns3_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_LO__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI__data__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_IDCODE_HI__data_MASK                                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                   0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                         0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                        0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                        0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                      0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                     0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                      0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                               0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                               0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                 0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                               0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                 0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                                0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                               0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                               0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                                0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                 0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                   0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                       0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                   0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                            0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__BG_EN__SHIFT                                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                              0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_IN_MASK                                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_REQ_OUT_MASK                                            0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_IN_MASK                                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__RES_ACK_OUT_MASK                                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ASIC_IN__BG_EN_MASK                                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                       0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                      0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                              0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                              0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                 0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                              0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                  0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                 0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                               0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                             0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_ANA_STAT__RESERVED_15_1_MASK                                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                    0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                         0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                           0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                           0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                         0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                         0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                              0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                    0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                              0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC40__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC40_MASK                                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__lpn_vreg_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__enable_reg__SHIFT                                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__cal_reg__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__reset_reg__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_enable_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__enable_reg_MASK                                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_cal_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__cal_reg_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__ovrd_reset_MASK                                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__reset_reg_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_right_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_left_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vp__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_gd__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_vp_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_gd_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__atb_select__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__NC76__SHIFT                                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_high_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__force_fine_low_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_atb_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_high_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__override_amp_low_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__atb_select_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__NC76_MASK                                                0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_atb__SHIFT                                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_atb_MASK                                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                         0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                         0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__NC7_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                      0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                             0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__NC76_MASK                                          0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__bypass_bg__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__vref_sel_fastreg__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__chop_en__SHIFT                                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__NC74__SHIFT                                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__RESERVED_15_8__SHIFT                                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__bypass_bg_MASK                                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__vref_sel_fastreg_MASK                                            0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__chop_en_MASK                                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__NC74_MASK                                                        0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_ANA_BG__RESERVED_15_8_MASK                                               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                    0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__STAT_MASK                                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                           0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                      0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                    0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                 0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                              0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                          0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE0_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE1_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE2_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANE3_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN2_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN3_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN4_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN5_B7_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B0_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B1_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B2_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B3_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B4_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B5_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R0__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R1__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R2__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R3__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R4__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R5__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R6__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R7__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R8__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R9__DATA_MASK                                         0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R10__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R11__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R12__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R13__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R14__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R15__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R16__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R17__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R18__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R19__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R20__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R21__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R22__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R23__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R24__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R25__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R26__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R27__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R28__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R29__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R30__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MEM_CMN6_B6_R31__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                          0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                      0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                     0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_LO__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI__data__SHIFT                                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_IDCODE_HI__data_MASK                                                0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN__SHIFT                                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10__SHIFT                               0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_DIV2_EN_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_REPEAT_CLK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                  0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__PHY_RESET_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__OVRD_EN_MASK                                        0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_REFCLK_OVRD_IN__RESERVED_15_10_MASK                                 0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                       0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_14_MASK                                0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                       0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN__SHIFT                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_REQ_IN_MASK                                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_ACK_IN_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RES_OVRD_EN_MASK                                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_5_MASK                                     0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN__SHIFT                                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RES_ACK_OUT_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__OVRD_EN_MASK                                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                     0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                  0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_10_MASK                                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13__SHIFT                              0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_MULTIPLIER_MASK                              0x1FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_13_MASK                                0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV2_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV8_CLK_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV10_CLK_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_MULTIPLIER_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_RANGE_MASK                               0x000EL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_FRACN_CTRL_MASK                              0x1FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_SSC_CLK_SEL_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_BANDWIDTH_MASK                               0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_11_MASK                                0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                  0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                  0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_IN__SHIFT                                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_OUT__SHIFT                                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_IN__SHIFT                                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_OUT__SHIFT                                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__BG_EN__SHIFT                                               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_CLK_DIV2_EN_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_REPEAT_CLK_EN_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                             0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_IN_MASK                                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_REQ_OUT_MASK                                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_IN_MASK                                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__RES_ACK_OUT_MASK                                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ASIC_IN__BG_EN_MASK                                                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                     0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN__SHIFT                     0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN__SHIFT                         0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV16P5_CLK_EN_MASK                       0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__MPLLA_DIV_CLK_EN_MASK                           0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__OVRD_SEL_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLA_OVRD_OUT__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL__SHIFT                                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_ANA_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_RST_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_CAL_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_EN_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_L_EN_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_OUTPUT_R_EN_MASK                          0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV8_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV10_CLK_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_FBCLK_EN_MASK                             0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_PHSEL_MASK                                0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__MPLLB_DIV_CLK_EN_MASK                           0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__OVRD_SEL_MASK                                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_MPLLB_OVRD_OUT__RESERVED_15_13_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                 0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                0x3FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RX_TERM_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_RX_TERM_OVRD_OUT__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RESERVED_15_1__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_ANA_STAT__RESERVED_15_1_MASK                                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLA_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE__SHIFT                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE__SHIFT                    0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__LOAD_CNT_MASK                          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_SKIPCAL_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__MPLL_EXTCAL_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CHKFRQ_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_COARSE_TUNE_MASK                   0x7F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL__EXT_CAL_DONE_MASK                      0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                        0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                          0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_15_10_MASK                   0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                      0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW_MASK                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__CHKFRQ_DONE_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                          0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_15_MASK                        0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD__SHIFT  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13__SHIFT  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__VCO_STABILIZATION_TIME_THRESHOLD_MASK  0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__MPLL_CAL_UPDATE_TIME_THRESHOLD_MASK  0x1E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD__RESERVED_15_13_MASK    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD__SHIFT  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__VCO_CLK_STABILIZATION_TIME_THRESHOLD_MASK  0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD__PCLK_EN_TIME_THRESHOLD_MASK  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD__SHIFT  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD__SHIFT  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__PCLK_DIS_TIME_THRESHOLD_MASK  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_VCO_PWRDN_TIME_THRESHOLD_MASK  0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD__MPLL_ANA_PWRUP_TIME_THRESHOLD_MASK  0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__SHIFT  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8__SHIFT  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBCLK_EN_TIME_THRESHOLD_MASK  0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_MASK  0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD__RESERVED_15_8_MASK  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__MPLL_COARSE_TUNE_VAL_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8__SHIFT   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__MPLL_SKIPCAL_COARSE_TUNE_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE__RESERVED_15_8_MASK     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL__SHIFT                                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__DTHR_MASK                                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__VAL_MASK                                        0x07FCL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__ZERO_FREQ_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__FRACN_CTRL_DIV_MASK                             0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_PHASE__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_CNT_INIT_MASK                             0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__FREQ_0_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_0__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_PK_MASK                                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__FREQ_1_OVRD_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_MPLLB_SSC_SS_FREQ_1__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC40__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__lpn_vreg__SHIFT                                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC40_MASK                                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__lpn_vreg_MASK                                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_MISC__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_enable__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__enable_reg__SHIFT                                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_cal__SHIFT                                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__cal_reg__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_reset__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__reset_reg__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_enable_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__enable_reg_MASK                                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_cal_MASK                                           0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__cal_reg_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_fb_clk_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__fb_clk_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__ovrd_reset_MASK                                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__reset_reg_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vco__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_right__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_left__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vp__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_cp__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_s__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_l__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vco_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_right_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_left_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_vp_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__override_vreg_cp_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_vco_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_s_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__meas_vreg_l_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_r__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vp__SHIFT                                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_gd__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ref__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_r_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_vp_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vreg_cp_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_vp_MASK                                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_gd_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_ctl_fine_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ctrl_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__meas_mag_ref_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_high__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_low__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_atb__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_high__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_low__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__atb_select__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__NC76__SHIFT                                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_high_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__force_fine_low_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_atb_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_high_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__override_amp_low_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__atb_select_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__NC76_MASK                                               0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp__SHIFT                                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_atb__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff__SHIFT                                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon__SHIFT                                      0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbf_MASK                                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_sel_atbp_MASK                                        0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_atb_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_chop_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_dac_mode_MASK                                        0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_x4_frcoff_MASK                                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__rt_en_frcon_MASK                                        0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw__SHIFT                                      0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__NC7__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_slowvreg_vref_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vph_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_fastvreg_vref_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_vp_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_gd_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_half_vph_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__atb_sw_MASK                                        0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__NC7_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__NC76__SHIFT                                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__hyst_ref_MASK                                     0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__vref_sel_slowvreg_MASK                            0x001CL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__temp_meas_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__NC76_MASK                                         0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_SWITCH_MISC_MEAS__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__bypass_bg__SHIFT                                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__vref_sel_fastreg__SHIFT                                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__chop_en__SHIFT                                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__NC74__SHIFT                                                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__RESERVED_15_8__SHIFT                                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__bypass_bg_MASK                                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__vref_sel_fastreg_MASK                                           0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__chop_en_MASK                                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__NC74_MASK                                                       0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_ANA_BG__RESERVED_15_8_MASK                                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__SKIP_RX_CAL_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_1_MASK                                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__STAT_MASK                                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                          0x0C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                     0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                               0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                         0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                   0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                     0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_3_MASK                              0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN__SHIFT                                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_0__EN_MASK                                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__IBOOST_LVL_MASK                                 0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__VBOOST_EN_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                         0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                             0x7E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                             0x1F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                              0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                             0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                               0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN__SHIFT                                       0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__EN_MASK                                         0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                       0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8__SHIFT                            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                         0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_8_MASK                              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                              0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                             0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN__SHIFT                                  0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC__SHIFT                                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN__SHIFT                                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_THRSHLD_MASK                                0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOS_LPFS_EN_MASK                                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_EN_MASK                                    0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__TERM_ACDC_MASK                                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__EN_MASK                                         0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12__SHIFT                        0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_12_MASK                          0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                 0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__EN_CTL_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                     0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                       0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                  0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL_MASK                                 0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                             0x0FC0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                             0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                             0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                     0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                       0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                      0x0600L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                               0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                             0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_THRSHLD_MASK                                0x0070L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__LOS_LPFS_EN_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                               0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10_MASK                             0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                         0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                              0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA1_GAIN_MASK                            0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA2_GAIN_MASK                            0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                           0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_CTLE_POLE_MASK                            0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                             0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                      0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                      0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                     0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__LOS_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                 0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5_MASK                             0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP2_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP3_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5__SHIFT                           0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP4_MASK                             0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP5_MASK                             0x3F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK               0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                   0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9__SHIFT                       0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                       0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                         0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                     0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_9_MASK                         0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_MASK                   0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_MASK                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                            0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                    0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME__SHIFT                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS__SHIFT                   0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET_MASK                      0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RESET_TIME_MASK                      0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_SERIAL_EN_TIME_MASK                  0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_FIFO_BYPASS_MASK                     0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                            0x7FE0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                  0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_LOS_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN_MASK            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN_MASK                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                  0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                   0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12__SHIFT                      0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_LOS_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN_MASK              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN_MASK                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                    0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                     0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                  0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_12_MASK                        0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT__SHIFT              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10__SHIFT                   0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_LOS_EN_TIME_MASK                     0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__SKIP_RX_LOS_EN_WAIT_MASK                0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RESERVED_15_10_MASK                     0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                   0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_RATE_TIME_MASK                       0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME_MASK                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN_MASK                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                    0x1F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                     0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME__SHIFT                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME__SHIFT                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CDR_EN_TIME_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_EN_TIME_MASK                   0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_DESER_DIS_TIME_MASK                  0x00C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RX_ANA_ADAPTATION_EN_MASK                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3__SHIFT                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_3_MASK                    0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                   0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                      0x01E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14__SHIFT                 0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL_MASK              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS_MASK              0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__RESERVED_15_14_MASK                   0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT               0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK              0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK               0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK           0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                 0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL__SHIFT                0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK          0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__FAST_RX_VCO_CAL_MASK                  0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_4_MASK                    0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                 0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                 0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                   0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                   0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                   0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN_MASK                        0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                      0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                     0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                        0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                        0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                    0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                     0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                      0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                       0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                    0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                    0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                   0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                  0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                     0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                              0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                 0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                 0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                            0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                               0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                               0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                              0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                            0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                              0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                       0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                       0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                    0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                             0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                  0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                        0x07FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                        0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                           0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                     0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                             0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                             0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                             0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                       0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                    0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                     0x0700L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                      0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                 0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                 0x0F80L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                 0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                 0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                              0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                               0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                 0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                 0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                            0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                             0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                           0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                            0x7C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                              0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                              0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                       0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                0x01C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                0x0E00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                         0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                      0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                  0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                        0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                        0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                        0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                          0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                          0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                 0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                      0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                  0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                   0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                        0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                    0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK          0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK          0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                 0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK           0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                  0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                      0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK           0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                               0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                               0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                        0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                            0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                            0x3C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                 0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                        0x003EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                            0x07C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                             0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                             0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                           0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                            0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                  0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                               0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                               0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                              0x03C0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                               0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                             0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                              0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                    0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                            0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                             0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                              0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                               0x0180L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                               0x1800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                               0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                    0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                  0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                         0x0038L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                       0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                           0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                          0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                       0x7FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                            0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_2_MASK                              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                             0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                 0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                               0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                           0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                 0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                             0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                   0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                   0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP__SHIFT              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN__SHIFT                  0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12__SHIFT                0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_CODEP_MASK                0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_TERM_UP_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__TX_CLK_LB_EN_MASK                    0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT__RESERVED_15_12_MASK                  0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN__SHIFT            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_CODE_MASK                 0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__TX_TERM_DN_OVRD_EN_MASK              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT__RESERVED_15_11_MASK                  0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_ATTEN_13_0_MASK                  0x7FFEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_ATTEN_29_14_MASK                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                       0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_ATTEN_34_30_MASK                 0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_UP_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_HALF_DN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                         0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6__SHIFT                         0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_HALF_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_PRE_QTR_MASK                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_HALF_MASK                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_QTR_MASK                    0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_6_MASK                           0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14__SHIFT                        0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_POST_MASK                        0x3FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__RESERVED_15_14_MASK                          0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                         0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                         0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                         0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                           0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                           0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                            0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_LOS_EN_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                        0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                   0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                   0x1FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                     0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                            0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                 0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                               0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                               0x03E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                              0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_SHORT_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                   0x6000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                  0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                            0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN__SHIFT                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                          0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                        0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA1_GAIN_MASK                      0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_VGA2_GAIN_MASK                      0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                            0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_POLE_MASK                         0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                        0x00F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                           0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                              0x0FF0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                             0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                      0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                      0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                             0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK            0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                     0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                     0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK              0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                    0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                             0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                             0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_LOS_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                               0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                               0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_0__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                 0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                  0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg__SHIFT                                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p__SHIFT                                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_clk_shift_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__clk_shift_reg_MASK                                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_m_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__meas_samp_p_MASK                                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__ovrd_vcm_hold_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__vcm_hold_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_up_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__pull_dn_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg__SHIFT                                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__data_en_reg__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg__SHIFT                                     0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_en__SHIFT                                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_tx_loopback_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__loopback_en_reg_MASK                                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__refgen_en_reg_MASK                                    0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_div_en_reg_MASK                                   0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__data_en_reg_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__clk_en_reg_MASK                                       0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__serial_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__ovrd_en_MASK                                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__drv_source_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus__SHIFT                                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vph__SHIFT                                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vptx__SHIFT                                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt__SHIFT                                      0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__drv_source_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__ovrd_alt_bus_MASK                                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vph_MASK                                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vptx_MASK                                          0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_lvt_MASK                                        0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__osc_vp_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__jtag_data_reg_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_gd__SHIFT                                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccm__SHIFT                                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccp__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vptx__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__override_regref_0__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg0__SHIFT                                          0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg1__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg_s__SHIFT                                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_gd_MASK                                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccm_MASK                                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vdccp_MASK                                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vptx_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__override_regref_0_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg0_MASK                                            0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg1_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__atb_vreg_s_MASK                                           0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_vcm__SHIFT                                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsm__SHIFT                                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsp__SHIFT                                           0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfm__SHIFT                                           0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfp__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_rxdetref__SHIFT                                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_nbias__SHIFT                                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_pbias__SHIFT                                          0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_vcm_MASK                                              0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsm_MASK                                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txsp_MASK                                             0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfm_MASK                                             0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_txfp_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_rxdetref_MASK                                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_nbias_MASK                                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__atb_pbias_MASK                                            0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__meas_atb_vph_half__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_s_enable__SHIFT                                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__override_vref_boost_ref__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_vref__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost__SHIFT                                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n__SHIFT                                0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__vboost_en_reg__SHIFT                                    0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__ovrd_vboost_en__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__RESERVED_15_8__SHIFT                                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__meas_atb_vph_half_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_s_enable_MASK                                       0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__override_vref_boost_ref_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_vref_MASK                                    0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__atb_vboost_MASK                                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__boost_vptx_mode_n_MASK                                  0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__vboost_en_reg_MASK                                      0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__ovrd_vboost_en_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_VBOOST__RESERVED_15_8_MASK                                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__term_code_dn_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_DN__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8__SHIFT                              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_ovrd_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__term_code_up_reg_MASK                             0x00FEL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_TERM_CODE_UP__RESERVED_15_8_MASK                                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg__SHIFT                            0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd__SHIFT                            0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8__SHIFT                               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__lfps_high_priority_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_up_reg_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__term_code_dn_reg_MASK                              0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_ovrd_MASK                              0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__iboost_code_MASK                                   0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_IBOOST_CODE__RESERVED_15_8_MASK                                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__override_regref_1__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg__SHIFT                                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en__SHIFT                                     0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg__SHIFT                               0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__override_regref_1_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__clk_lb_en_reg_MASK                                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_lb_en_MASK                                       0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mpllb_clk_en_reg_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__mplla_clk_en_reg_MASK                                 0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_mpllab_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__word_clk_en_reg_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__ovrd_word_clk_en_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__nc__SHIFT                                                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_pmos__SHIFT                                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_nmos__SHIFT                                           0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__meas_atb_bias_vptx__SHIFT                                 0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__override_rxdetref__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__nc_MASK                                                   0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_pmos_MASK                                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__osc_nmos_MASK                                             0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__meas_atb_bias_vptx_MASK                                   0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__override_rxdetref_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_TX_MISC__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__iq_phase_adjust_reg_MASK                            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_vp_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__meas_atb_rx_scope_reg_MASK                          0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__master_atb_en_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_IQSKEW__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__data_rate_reg__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc__SHIFT                                  0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg__SHIFT                            0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg__SHIFT                                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__data_rate_reg_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__meas_atb_vdcc_MASK                                    0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_rx_loopback_clk_MASK                             0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__rx_loopback_clk_reg_MASK                              0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__ovrd_dccandafe_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__dcc_en_reg_MASK                                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_DCC_OVRD__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__los_en_reg__SHIFT                                    0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_acjt_en_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__acjt_en_reg_MASK                                     0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_clk_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__clk_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_los_en_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__los_en_reg_MASK                                      0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__ovrd_afe_en_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__afe_en_reg_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_slc__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_scope__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux__SHIFT                             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_samp_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_slc_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_scope_MASK                          0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__override_regref_clk_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__meas_atb_cal_mux_MASK                               0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                  0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__meas_atb_rx__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg__SHIFT                                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_even_reg__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8__SHIFT                                   0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__meas_atb_rx_MASK                                       0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_odd_reg_MASK                                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_even_reg_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_fall_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__phdet_rise_reg_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CDR_AFE__RESERVED_15_8_MASK                                     0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__NC10__SHIFT                                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg__SHIFT                                    0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en__SHIFT                              0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg__SHIFT                               0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en__SHIFT                              0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__NC10_MASK                                            0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_dfe_en_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__dfe_en_reg_MASK                                      0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_deserial_en_MASK                                0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__deserial_en_reg_MASK                                 0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__ovrd_loopback_en_MASK                                0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__loopback_en_reg_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__NC32__SHIFT                                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg__SHIFT                            0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__shor_en_reg__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_word_clk_en_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__word_clk_en_reg_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__NC32_MASK                                            0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__rx_los_lfps_en_reg_MASK                              0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_los_lfps_en_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__shor_en_reg_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__ovrd_short_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_MISC_OVRD__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u__SHIFT                              0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atv_vco_200u_MASK                                0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__meas_atb_vibias_vco_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__cal_muxa_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__ovrd_cal_muxa_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXA__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__NC0__SHIFT                                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos__SHIFT                                  0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__NC0_MASK                                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__meas_atb_rx_MASK                                     0x007EL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__atb_frc_vlos_MASK                                    0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc__SHIFT                                 0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_vosc_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_vco_gd_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_ovrd_cdr_en_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_scope_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_slc_MASK                                   0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_clk_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_vreg_s_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__meas_atb_gd_MASK                                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                   0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__dfe_taps_en_reg_MASK                                  0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_dfe_taps_en_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__cal_muxb_sel_reg_MASK                                 0x007CL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__ovrd_cal_muxb_sel_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_CAL_MUXB__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__NC20__SHIFT                                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust__SHIFT                               0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_gd_en_reg__SHIFT                                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_dc_en_reg__SHIFT                                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en__SHIFT                                 0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__RESERVED_15_8__SHIFT                                      0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__NC20_MASK                                                 0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_iq_phase_adjust_MASK                                 0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_gd_en_reg_MASK                                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_gd_en_MASK                                   0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__rx_term_dc_en_reg_MASK                                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__ovrd_rx_term_dc_en_MASK                                   0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_TERM__RESERVED_15_8_MASK                                        0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg__SHIFT                           0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_o_reg_MASK                             0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__rx_slicer_ctrl_e_reg_MASK                             0x00F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc__SHIFT                              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp__SHIFT                          0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe__SHIFT                              0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc__SHIFT                                0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8__SHIFT                                  0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_rx_slicer_ctrl_reg_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_iqc_vref_sel_MASK                                0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_scope_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_iqc_MASK                                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_byp_MASK                            0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__meas_atb_vreg_dfe_MASK                                0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_scope_MASK                            0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__ovrd_regref_iqc_MASK                                  0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_LANEX_ANA_RX_ATB_VREG__RESERVED_15_8_MASK                                    0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN2_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN3_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN4_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN5_B7_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B0_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B1_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B2_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B3_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B4_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B5_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R0__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R1__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R2__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R3__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R4__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R5__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R6__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R7__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R8__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R9__DATA_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R10__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R11__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R12__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R13__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R14__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R15__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R16__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R17__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R18__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R19__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R20__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R21__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R22__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R23__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R24__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R25__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R26__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R27__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R28__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R29__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R30__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MEM_CMN6_B6_R31__DATA_MASK                                       0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_CMN_CTL__RESERVED_15_1_MASK                                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_CTL_OVRD_IN__MPLLA_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__MPLLA_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLA_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                         0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                          0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_BW_OVRD_IN__RESERVED_15_12_MASK                            0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN__SHIFT              0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_RANGE_MASK                      0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_FRACN_CTRL_MASK                     0x0FF8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CLK_SEL_MASK                    0x7000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_CTL_OVRD_IN__MPLLB_SSC_CTL_OVRD_EN_MASK                0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN__SHIFT                0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_VAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__MPLLB_SSC_EN_OVRD_EN_MASK                  0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWCMNX_DIG_MPLLB_SSC_EN_OVRD_IN__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                   0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                 0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                               0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                      0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                      0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                               0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13__SHIFT                        0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                  0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                     0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                   0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                    0x00E0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                 0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                        0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                        0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                 0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RESERVED_15_13_MASK                          0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                  0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                   0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                  0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                 0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                  0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13__SHIFT                      0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                    0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                     0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                    0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                     0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                   0x0F00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                    0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_13_MASK                        0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                   0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                              0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                       0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                              0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                      0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                    0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                     0x0380L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                  0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                         0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                         0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                               0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                           0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                 0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                 0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                   0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                               0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                          0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                    0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                   0x000CL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                  0x0030L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                     0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                 0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                            0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                            0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                           0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_4_MASK                         0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                  0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT             0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                       0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                    0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                  0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK               0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN__SHIFT              0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                     0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                  0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN__SHIFT                   0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT__SHIFT                          0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN__SHIFT                        0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_VAL_MASK               0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RX_LOS_THRSHLD_OVRD_EN_MASK                0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                       0x03F0L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                    0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_MASK                             0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_REQ_OVRD_EN_MASK                     0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__ADAPT_CONT_MASK                            0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__OFFCAN_CONT_MASK                           0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__CONT_OVRD_EN_MASK                          0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                  0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                 0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                              0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                             0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                  0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                         0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                     0x0006L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                    0x0018L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                   0x0060L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                      0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                               0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                    0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                           0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6__SHIFT                        0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_6_MASK                          0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                       0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                             0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                         0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                         0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                        0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                             0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                           0x0078L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                           0x0780L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                          0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                       0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                           0x0007L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                            0x07F8L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                         0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                               0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                 0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                          0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                       0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                          0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                         0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                          0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                         0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                        0x0003L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                        0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                            0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                             0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                          0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                            0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14__SHIFT                         0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                             0x07FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                               0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                            0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                              0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_14_MASK                           0xC000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                 0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                  0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                              0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                           0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                           0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                           0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                      0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                    0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                  0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                               0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                             0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                             0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                             0xF800L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_INIT_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__CMNCAL_DONE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_FSM_CMNCAL_STATUS__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__AFE_CTLE_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST_MASK                 0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_AFE_VGA1_IDAC_OFST__RESERVED_15_8_MASK                      0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__DFE_SUMMER_EVEN_IDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__DFE_SUMMER_ODD_IDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RX_PHSADJ_LIN_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_LIN__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RX_PHSADJ_MAP_MASK                           0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_PHSADJ_MAP__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT          0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK            0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT            0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST_MASK  0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK              0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT             0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST_MASK   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK               0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT              0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK     0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT               0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK       0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                 0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                    0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RX_IQ_PHASE_ADJUST_MASK                 0x007FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                      0xFF80L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__MPLLA_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                     0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__MPLLB_COARSE_TUNE_MASK                   0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                       0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RTUNE_RX_VAL_MASK                             0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_RX_VAL__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RTUNE_TXDN_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXDN_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL__SHIFT                       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10__SHIFT                       0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RTUNE_TXUP_VAL_MASK                         0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RTUNE_TXUP_VAL__RESERVED_15_10_MASK                         0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__INIT_PWRUP_DONE_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_INIT_PWRUP_DONE__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8__SHIFT                           0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                              0x00FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_ATT__RESERVED_15_8_MASK                             0xFF00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10__SHIFT                          0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                              0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_VGA__RESERVED_15_10_MASK                            0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                     0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                      0x03FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                       0x1C00L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_CTLE__RESERVED_15_13_MASK                           0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                     0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                    0x1FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                       0xE000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                         0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RX_ADAPT_DONE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADAPT_DONE__RESERVED_15_1_MASK                           0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                          0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                          0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                       0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                           0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                        0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                        0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP__SHIFT                                 0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                         0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET__SHIFT                            0xb
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                            0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                         0xd
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                          0xe
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15__SHIFT                           0xf
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_ADAPT_MASK                              0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                            0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                            0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                         0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                             0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                          0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                          0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_SUP_MASK                                   0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                           0x0400L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_TX_RXDET_MASK                              0x0800L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_PWRUP_MASK                              0x1000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                           0x2000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                            0x4000L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_FAST_FLAGS__RESERVED_15_15_MASK                             0x8000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                     0xc
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                    0x0FFFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                       0xF000L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT            0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK              0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                     0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                    0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK               0x000FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                      0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_INIT_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__LANE_CMNCAL_DONE_MASK                   0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_LANE_CMNCAL_STATUS__RESERVED_15_2_MASK                      0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_0__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_1__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_2__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_3__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_4__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_5__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_6__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL__SHIFT                                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_AON_ADPT_CTL_7__VAL_MASK                                        0xFFFFL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                      0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                        0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                          0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                     0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                       0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT               0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                 0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                    0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                   0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                     0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                      0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                   0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT       0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT              0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK         0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                      0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                   0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                   0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                       0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6__SHIFT                          0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                        0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                     0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                     0x0010L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                         0x0020L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_6_MASK                            0xFFC0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                    0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                        0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                       0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                      0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                          0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                         0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                       0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                      0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                    0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                    0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                         0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                        0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                        0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                            0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                            0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                          0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                           0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                           0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK__SHIFT                             0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3__SHIFT                         0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                             0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                             0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RTUNE_ACK_MASK                               0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_3_MASK                           0xFFF8L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                      0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                       0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                    0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                     0x3
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4__SHIFT                        0x4
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                        0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                         0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                      0x0004L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                       0x0008L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_4_MASK                          0xFFF0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                          0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                            0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                    0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                     0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                      0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                       0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                 0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                     0x6
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                     0x7
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                    0x8
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                     0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10__SHIFT                        0xa
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                   0x003FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                       0x0040L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                       0x0080L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                      0x0100L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                       0x0200L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_10_MASK                          0xFC00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                             0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                            0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5__SHIFT                         0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                               0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                              0x001EL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_5_MASK                           0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                        0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                         0x2
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                          0x0002L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                           0xFFFCL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                  0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                    0x9
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                    0x01FFL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                      0xFE00L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT          0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT             0x5
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK            0x001FL
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK               0xFFE0L
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                        0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                 0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                          0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                   0xFFFEL
//DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                         0x0
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                  0x1
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                           0x0001L
#define DWC_E12MP_PHY_X4_NS_X4_3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                    0xFFFEL


// addressBlock: nbio_lcu_kpfifo_kpfifo3_kpfifo_dir
//KPFIFO3_PRI_TX_FIFO_HSCID
#define KPFIFO3_PRI_TX_FIFO_HSCID__HwRev__SHIFT                                                               0x0
#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMinVer__SHIFT                                                            0x6
#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMajVer__SHIFT                                                            0xd
#define KPFIFO3_PRI_TX_FIFO_HSCID__HwRev_MASK                                                                 0x0000003FL
#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMinVer_MASK                                                              0x00001FC0L
#define KPFIFO3_PRI_TX_FIFO_HSCID__HwMajVer_MASK                                                              0x000FE000L
//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__LinkID__SHIFT                                                     0x0
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth__SHIFT                                                  0x10
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__Standalone__SHIFT                                                 0x1a
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__LinkID_MASK                                                       0x000000FFL
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__Standalone_MASK                                                   0x04000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_0__HwDebug4_MASK                                                     0x80000000L
//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__LinkID__SHIFT                                                     0x0
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth__SHIFT                                                  0x10
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__Standalone__SHIFT                                                 0x1a
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__LinkID_MASK                                                       0x000000FFL
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__Standalone_MASK                                                   0x04000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_1__HwDebug4_MASK                                                     0x80000000L
//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__LinkID__SHIFT                                                     0x0
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth__SHIFT                                                  0x10
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__Standalone__SHIFT                                                 0x1a
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__LinkID_MASK                                                       0x000000FFL
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__Standalone_MASK                                                   0x04000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_2__HwDebug4_MASK                                                     0x80000000L
//KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__LinkID__SHIFT                                                     0x0
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset__SHIFT                                            0x8
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth__SHIFT                                                  0x10
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass__SHIFT                                                 0x18
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode__SHIFT                                               0x19
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__Standalone__SHIFT                                                 0x1a
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0__SHIFT                                                   0x1b
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1__SHIFT                                                   0x1c
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2__SHIFT                                                   0x1d
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3__SHIFT                                                   0x1e
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4__SHIFT                                                   0x1f
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__LinkID_MASK                                                       0x000000FFL
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFORdPtrOffset_MASK                                              0x0000FF00L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFODepth_MASK                                                    0x00FF0000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOBypass_MASK                                                   0x01000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__FIFOInitMode_MASK                                                 0x02000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__Standalone_MASK                                                   0x04000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug0_MASK                                                     0x08000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug1_MASK                                                     0x10000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug2_MASK                                                     0x20000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug3_MASK                                                     0x40000000L
#define KPFIFO3_PRI_TX_FIFO_CONTROL_LANE_3__HwDebug4_MASK                                                     0x80000000L
//KPFIFO3_PCS_PMA_SOFT_RESET
#define KPFIFO3_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy__SHIFT                                           0x0
#define KPFIFO3_PCS_PMA_SOFT_RESET__KPFIFO_PHY_soft_ResetPhy_MASK                                             0x00000001L


// addressBlock: nbio_lcu_kpnp_kpnp3_kpnp_dir
//KPNP_SNPS3_KPNP_HWSCVER
#define KPNP_SNPS3_KPNP_HWSCVER__hw_revision__SHIFT                                                           0x0
#define KPNP_SNPS3_KPNP_HWSCVER__hw_minor_version_number__SHIFT                                               0x6
#define KPNP_SNPS3_KPNP_HWSCVER__hw_major_version_number__SHIFT                                               0xd
#define KPNP_SNPS3_KPNP_HWSCVER__hw_revision_MASK                                                             0x0000003FL
#define KPNP_SNPS3_KPNP_HWSCVER__hw_minor_version_number_MASK                                                 0x00001FC0L
#define KPNP_SNPS3_KPNP_HWSCVER__hw_major_version_number_MASK                                                 0x000FE000L
//KPNP_SNPS3_KPNP_PHY_INFO
#define KPNP_SNPS3_KPNP_PHY_INFO__HwRev__SHIFT                                                                0x0
#define KPNP_SNPS3_KPNP_PHY_INFO__PHYVer__SHIFT                                                               0x6
#define KPNP_SNPS3_KPNP_PHY_INFO__Technology__SHIFT                                                           0xd
#define KPNP_SNPS3_KPNP_PHY_INFO__Type__SHIFT                                                                 0x14
#define KPNP_SNPS3_KPNP_PHY_INFO__VendorID__SHIFT                                                             0x1a
#define KPNP_SNPS3_KPNP_PHY_INFO__HwRev_MASK                                                                  0x0000003FL
#define KPNP_SNPS3_KPNP_PHY_INFO__PHYVer_MASK                                                                 0x00001FC0L
#define KPNP_SNPS3_KPNP_PHY_INFO__Technology_MASK                                                             0x000FE000L
#define KPNP_SNPS3_KPNP_PHY_INFO__Type_MASK                                                                   0x03F00000L
#define KPNP_SNPS3_KPNP_PHY_INFO__VendorID_MASK                                                               0xFC000000L
//KPNP_SNPS3_KPNP_LANE_ID
#define KPNP_SNPS3_KPNP_LANE_ID__NodeStartLane__SHIFT                                                         0x0
#define KPNP_SNPS3_KPNP_LANE_ID__NodeEndLane__SHIFT                                                           0x8
#define KPNP_SNPS3_KPNP_LANE_ID__NodeStartLane_MASK                                                           0x000000FFL
#define KPNP_SNPS3_KPNP_LANE_ID__NodeEndLane_MASK                                                             0x0000FF00L
//KPNP_SNPS3_KPNP_LANE_REQ_CONTROL
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0TxReq__SHIFT                                                     0x0
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0RxReq__SHIFT                                                     0x1
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1TxReq__SHIFT                                                     0x2
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1RxReq__SHIFT                                                     0x3
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2TxReq__SHIFT                                                     0x4
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2RxReq__SHIFT                                                     0x5
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3TxReq__SHIFT                                                     0x6
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3RxReq__SHIFT                                                     0x7
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0TxReq_MASK                                                       0x00000001L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln0RxReq_MASK                                                       0x00000002L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1TxReq_MASK                                                       0x00000004L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln1RxReq_MASK                                                       0x00000008L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2TxReq_MASK                                                       0x00000010L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln2RxReq_MASK                                                       0x00000020L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3TxReq_MASK                                                       0x00000040L
#define KPNP_SNPS3_KPNP_LANE_REQ_CONTROL__Ln3RxReq_MASK                                                       0x00000080L
//KPNP_SNPS3_KPNP_LANE_REQ_STATUS
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0TxAck__SHIFT                                                      0x0
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0RxAck__SHIFT                                                      0x1
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1TxAck__SHIFT                                                      0x2
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1RxAck__SHIFT                                                      0x3
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2TxAck__SHIFT                                                      0x4
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2RxAck__SHIFT                                                      0x5
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3TxAck__SHIFT                                                      0x6
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3RxAck__SHIFT                                                      0x7
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0TxAck_MASK                                                        0x00000001L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln0RxAck_MASK                                                        0x00000002L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1TxAck_MASK                                                        0x00000004L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln1RxAck_MASK                                                        0x00000008L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2TxAck_MASK                                                        0x00000010L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln2RxAck_MASK                                                        0x00000020L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3TxAck_MASK                                                        0x00000040L
#define KPNP_SNPS3_KPNP_LANE_REQ_STATUS__Ln3RxAck_MASK                                                        0x00000080L
//KPNP_SNPS3_KPNP_PMA_CONTROL0
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__ref_use_pad__SHIFT                                                      0x0
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Tx_Disable__SHIFT                                                   0x10
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Rx_Disable__SHIFT                                                   0x11
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Tx_Disable__SHIFT                                                   0x12
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Rx_Disable__SHIFT                                                   0x13
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Tx_Disable__SHIFT                                                   0x14
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Rx_Disable__SHIFT                                                   0x15
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Tx_Disable__SHIFT                                                   0x16
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Rx_Disable__SHIFT                                                   0x17
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__ref_use_pad_MASK                                                        0x00000001L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Tx_Disable_MASK                                                     0x00010000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln0_Rx_Disable_MASK                                                     0x00020000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Tx_Disable_MASK                                                     0x00040000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln1_Rx_Disable_MASK                                                     0x00080000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Tx_Disable_MASK                                                     0x00100000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln2_Rx_Disable_MASK                                                     0x00200000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Tx_Disable_MASK                                                     0x00400000L
#define KPNP_SNPS3_KPNP_PMA_CONTROL0__Ln3_Rx_Disable_MASK                                                     0x00800000L
//KPNP_SNPS3_KPNP_PMA_CONTROL1
#define KPNP_SNPS3_KPNP_PMA_CONTROL1__rx_vref_ctrl__SHIFT                                                     0x0
#define KPNP_SNPS3_KPNP_PMA_CONTROL1__tx_vboost_lvl__SHIFT                                                    0x5
#define KPNP_SNPS3_KPNP_PMA_CONTROL1__rx_vref_ctrl_MASK                                                       0x0000001FL
#define KPNP_SNPS3_KPNP_PMA_CONTROL1__tx_vboost_lvl_MASK                                                      0x000000E0L
//KPNP_SNPS3_KPNP_PMA_CONTROL2
#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Disable__SHIFT                                               0x0
#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Mode__SHIFT                                                  0x1
#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Time_Resolution__SHIFT                                       0x2
#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Disable_MASK                                                 0x00000001L
#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Mode_MASK                                                    0x00000002L
#define KPNP_SNPS3_KPNP_PMA_CONTROL2__Staggering_Time_Resolution_MASK                                         0x0000001CL
//KPNP_SNPS3_KPNP_PHY_SOFT_RESET
#define KPNP_SNPS3_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset__SHIFT                                                 0x0
#define KPNP_SNPS3_KPNP_PHY_SOFT_RESET__Phy_Soft_Reset_MASK                                                   0x00000001L
//KPNP_SNPS3_KPNP_LANE_SOFT_RESET
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset__SHIFT                                             0x0
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset__SHIFT                                             0x1
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset__SHIFT                                             0x2
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset__SHIFT                                             0x3
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset__SHIFT                                             0x4
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset__SHIFT                                             0x5
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset__SHIFT                                             0x6
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset__SHIFT                                             0x7
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Tx_Soft_Reset_MASK                                               0x00000001L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln0_Rx_Soft_Reset_MASK                                               0x00000002L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Tx_Soft_Reset_MASK                                               0x00000004L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln1_Rx_Soft_Reset_MASK                                               0x00000008L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Tx_Soft_Reset_MASK                                               0x00000010L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln2_Rx_Soft_Reset_MASK                                               0x00000020L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Tx_Soft_Reset_MASK                                               0x00000040L
#define KPNP_SNPS3_KPNP_LANE_SOFT_RESET__Ln3_Rx_Soft_Reset_MASK                                               0x00000080L
//KPNP_SNPS3_REG_RST_CTRL
#define KPNP_SNPS3_REG_RST_CTRL__reset_regs_when_dxio_phy_rst__SHIFT                                          0x0
#define KPNP_SNPS3_REG_RST_CTRL__reset_regs_when_dxio_phy_rst_MASK                                            0x00000001L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF0_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF0_MM_DATA
#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF0_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF1_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF1_MM_DATA
#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF1_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF2_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF2_MM_DATA
#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF2_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF3_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF3_MM_DATA
#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF3_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF4_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF4_MM_DATA
#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF4_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF5_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF5_MM_DATA
#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF5_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF6_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF6_MM_DATA
#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF6_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF7_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF7_MM_DATA
#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF7_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF8_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF8_MM_DATA
#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF8_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF9_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET__SHIFT                                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER__SHIFT                                                         0x1f
#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_OFFSET_MASK                                                         0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX__MM_APER_MASK                                                           0x80000000L
//BIF_BX_DEV0_EPF0_VF9_MM_DATA
#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA__SHIFT                                                          0x0
#define BIF_BX_DEV0_EPF0_VF9_MM_DATA__MM_DATA_MASK                                                            0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                 0x0
#define BIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                   0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                      0x10
#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                        0x00010000L
//BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                   0x1
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                      0x2
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                          0x3
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                0x10
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                             0x11
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                0x12
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                    0x13
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                        0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                        0x00000004L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                            0x00000008L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                  0x00010000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                               0x00020000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                  0x00040000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                      0x00080000L
//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK    0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT            0x0
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT          0x1
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT          0x8
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK              0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK            0x00000002L
#define BIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK            0x000FFF00L
//BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                          0x0
#define BIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                            0x00000001L
//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                    0x0
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                    0x1
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                    0x2
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                    0x3
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                    0x4
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                    0x5
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                    0x6
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                    0x7
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                    0x8
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                    0x9
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                  0xa
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                  0xb
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP0_MASK                                                      0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP1_MASK                                                      0x00000002L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP2_MASK                                                      0x00000004L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP3_MASK                                                      0x00000008L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP4_MASK                                                      0x00000010L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP5_MASK                                                      0x00000020L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP6_MASK                                                      0x00000040L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP7_MASK                                                      0x00000080L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP8_MASK                                                      0x00000100L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__CP9_MASK                                                      0x00000200L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                    0x00000400L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                    0x00000800L
//BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                  0x0
#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                    0x00000002L
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                       0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                         0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                            0x8
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                              0x9
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                0x00000002L
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                              0x00000100L
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                0x00000200L
//BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                            0x0
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                              0x1
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                0x00000002L
//BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                            0x0
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                          0x1
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                               0x8
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                              0xf
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                              0x17
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                0x18
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                0x19
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                              0x00000001L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                            0x00000002L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                 0x00000F00L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                0x00008000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                 0x000F0000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                0x00800000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                  0x01000000L
#define BIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                  0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF10_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET__SHIFT                                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER__SHIFT                                                        0x1f
#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_OFFSET_MASK                                                        0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX__MM_APER_MASK                                                          0x80000000L
//BIF_BX_DEV0_EPF0_VF10_MM_DATA
#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA__SHIFT                                                         0x0
#define BIF_BX_DEV0_EPF0_VF10_MM_DATA__MM_DATA_MASK                                                           0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                0x0
#define BIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                     0x10
#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                       0x00010000L
//BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                     0x0
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                     0x2
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                         0x3
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                            0x11
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                               0x12
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                   0x13
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                       0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                       0x00000004L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                           0x00000008L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                 0x00010000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                              0x00020000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                 0x00040000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                     0x00080000L
//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK   0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT           0x0
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT         0x1
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT         0x8
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK             0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK           0x00000002L
#define BIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK           0x000FFF00L
//BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                  0x0
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                  0x1
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                  0x2
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                  0x3
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                  0x4
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                  0x5
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                  0x6
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                  0x7
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                  0x8
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                  0x9
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                0xa
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                0xb
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP0_MASK                                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP1_MASK                                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP2_MASK                                                    0x00000004L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP3_MASK                                                    0x00000008L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP4_MASK                                                    0x00000010L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP5_MASK                                                    0x00000020L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP6_MASK                                                    0x00000040L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP7_MASK                                                    0x00000080L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP8_MASK                                                    0x00000100L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__CP9_MASK                                                    0x00000200L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                  0x00000400L
#define BIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                  0x00000800L
//BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                 0x0
#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                 0x1
#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                   0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                   0x00000002L
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                           0x8
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                             0x9
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                               0x00000002L
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                             0x00000100L
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                               0x00000200L
//BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                               0x00000002L
//BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                           0x0
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                         0x1
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                              0x8
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                             0xf
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                              0x10
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                             0x17
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                               0x18
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                               0x19
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                           0x00000002L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                0x00000F00L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                               0x00008000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                0x000F0000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                               0x00800000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                 0x01000000L
#define BIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                 0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF11_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET__SHIFT                                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER__SHIFT                                                        0x1f
#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_OFFSET_MASK                                                        0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX__MM_APER_MASK                                                          0x80000000L
//BIF_BX_DEV0_EPF0_VF11_MM_DATA
#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA__SHIFT                                                         0x0
#define BIF_BX_DEV0_EPF0_VF11_MM_DATA__MM_DATA_MASK                                                           0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                0x0
#define BIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                     0x10
#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                       0x00010000L
//BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                     0x0
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                     0x2
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                         0x3
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                            0x11
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                               0x12
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                   0x13
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                       0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                       0x00000004L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                           0x00000008L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                 0x00010000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                              0x00020000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                 0x00040000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                     0x00080000L
//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK   0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT           0x0
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT         0x1
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT         0x8
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK             0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK           0x00000002L
#define BIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK           0x000FFF00L
//BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                  0x0
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                  0x1
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                  0x2
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                  0x3
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                  0x4
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                  0x5
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                  0x6
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                  0x7
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                  0x8
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                  0x9
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                0xa
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                0xb
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP0_MASK                                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP1_MASK                                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP2_MASK                                                    0x00000004L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP3_MASK                                                    0x00000008L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP4_MASK                                                    0x00000010L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP5_MASK                                                    0x00000020L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP6_MASK                                                    0x00000040L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP7_MASK                                                    0x00000080L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP8_MASK                                                    0x00000100L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__CP9_MASK                                                    0x00000200L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                  0x00000400L
#define BIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                  0x00000800L
//BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                 0x0
#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                 0x1
#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                   0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                   0x00000002L
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                           0x8
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                             0x9
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                               0x00000002L
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                             0x00000100L
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                               0x00000200L
//BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                               0x00000002L
//BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                           0x0
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                         0x1
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                              0x8
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                             0xf
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                              0x10
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                             0x17
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                               0x18
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                               0x19
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                           0x00000002L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                0x00000F00L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                               0x00008000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                0x000F0000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                               0x00800000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                 0x01000000L
#define BIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                 0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF12_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET__SHIFT                                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER__SHIFT                                                        0x1f
#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_OFFSET_MASK                                                        0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX__MM_APER_MASK                                                          0x80000000L
//BIF_BX_DEV0_EPF0_VF12_MM_DATA
#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA__SHIFT                                                         0x0
#define BIF_BX_DEV0_EPF0_VF12_MM_DATA__MM_DATA_MASK                                                           0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                0x0
#define BIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                     0x10
#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                       0x00010000L
//BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                     0x0
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                     0x2
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                         0x3
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                            0x11
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                               0x12
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                   0x13
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                       0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                       0x00000004L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                           0x00000008L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                 0x00010000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                              0x00020000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                 0x00040000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                     0x00080000L
//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK   0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT           0x0
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT         0x1
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT         0x8
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK             0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK           0x00000002L
#define BIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK           0x000FFF00L
//BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                  0x0
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                  0x1
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                  0x2
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                  0x3
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                  0x4
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                  0x5
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                  0x6
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                  0x7
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                  0x8
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                  0x9
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                0xa
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                0xb
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP0_MASK                                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP1_MASK                                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP2_MASK                                                    0x00000004L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP3_MASK                                                    0x00000008L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP4_MASK                                                    0x00000010L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP5_MASK                                                    0x00000020L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP6_MASK                                                    0x00000040L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP7_MASK                                                    0x00000080L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP8_MASK                                                    0x00000100L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__CP9_MASK                                                    0x00000200L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                  0x00000400L
#define BIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                  0x00000800L
//BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                 0x0
#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                 0x1
#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                   0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                   0x00000002L
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                           0x8
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                             0x9
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                               0x00000002L
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                             0x00000100L
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                               0x00000200L
//BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                               0x00000002L
//BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                           0x0
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                         0x1
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                              0x8
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                             0xf
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                              0x10
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                             0x17
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                               0x18
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                               0x19
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                           0x00000002L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                0x00000F00L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                               0x00008000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                0x000F0000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                               0x00800000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                 0x01000000L
#define BIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                 0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF13_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET__SHIFT                                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER__SHIFT                                                        0x1f
#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_OFFSET_MASK                                                        0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX__MM_APER_MASK                                                          0x80000000L
//BIF_BX_DEV0_EPF0_VF13_MM_DATA
#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA__SHIFT                                                         0x0
#define BIF_BX_DEV0_EPF0_VF13_MM_DATA__MM_DATA_MASK                                                           0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                0x0
#define BIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                     0x10
#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                       0x00010000L
//BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                     0x0
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                     0x2
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                         0x3
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                            0x11
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                               0x12
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                   0x13
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                       0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                       0x00000004L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                           0x00000008L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                 0x00010000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                              0x00020000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                 0x00040000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                     0x00080000L
//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK   0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT           0x0
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT         0x1
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT         0x8
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK             0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK           0x00000002L
#define BIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK           0x000FFF00L
//BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                  0x0
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                  0x1
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                  0x2
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                  0x3
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                  0x4
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                  0x5
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                  0x6
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                  0x7
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                  0x8
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                  0x9
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                0xa
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                0xb
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP0_MASK                                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP1_MASK                                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP2_MASK                                                    0x00000004L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP3_MASK                                                    0x00000008L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP4_MASK                                                    0x00000010L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP5_MASK                                                    0x00000020L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP6_MASK                                                    0x00000040L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP7_MASK                                                    0x00000080L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP8_MASK                                                    0x00000100L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__CP9_MASK                                                    0x00000200L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                  0x00000400L
#define BIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                  0x00000800L
//BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                 0x0
#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                 0x1
#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                   0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                   0x00000002L
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                           0x8
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                             0x9
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                               0x00000002L
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                             0x00000100L
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                               0x00000200L
//BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                               0x00000002L
//BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                           0x0
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                         0x1
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                              0x8
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                             0xf
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                              0x10
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                             0x17
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                               0x18
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                               0x19
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                           0x00000002L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                0x00000F00L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                               0x00008000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                0x000F0000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                               0x00800000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                 0x01000000L
#define BIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                 0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF14_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET__SHIFT                                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER__SHIFT                                                        0x1f
#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_OFFSET_MASK                                                        0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX__MM_APER_MASK                                                          0x80000000L
//BIF_BX_DEV0_EPF0_VF14_MM_DATA
#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA__SHIFT                                                         0x0
#define BIF_BX_DEV0_EPF0_VF14_MM_DATA__MM_DATA_MASK                                                           0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                0x0
#define BIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                     0x10
#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                       0x00010000L
//BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                     0x0
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                     0x2
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                         0x3
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                            0x11
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                               0x12
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                   0x13
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                       0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                       0x00000004L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                           0x00000008L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                 0x00010000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                              0x00020000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                 0x00040000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                     0x00080000L
//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK   0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT           0x0
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT         0x1
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT         0x8
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK             0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK           0x00000002L
#define BIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK           0x000FFF00L
//BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                  0x0
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                  0x1
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                  0x2
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                  0x3
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                  0x4
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                  0x5
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                  0x6
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                  0x7
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                  0x8
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                  0x9
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                0xa
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                0xb
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP0_MASK                                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP1_MASK                                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP2_MASK                                                    0x00000004L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP3_MASK                                                    0x00000008L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP4_MASK                                                    0x00000010L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP5_MASK                                                    0x00000020L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP6_MASK                                                    0x00000040L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP7_MASK                                                    0x00000080L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP8_MASK                                                    0x00000100L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__CP9_MASK                                                    0x00000200L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                  0x00000400L
#define BIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                  0x00000800L
//BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                 0x0
#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                 0x1
#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                   0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                   0x00000002L
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                           0x8
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                             0x9
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                               0x00000002L
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                             0x00000100L
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                               0x00000200L
//BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                               0x00000002L
//BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                           0x0
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                         0x1
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                              0x8
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                             0xf
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                              0x10
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                             0x17
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                               0x18
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                               0x19
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                           0x00000002L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                0x00000F00L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                               0x00008000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                0x000F0000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                               0x00800000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                 0x01000000L
#define BIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                 0x02000000L


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
//BIF_BX_DEV0_EPF0_VF15_MM_INDEX
#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET__SHIFT                                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER__SHIFT                                                        0x1f
#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_OFFSET_MASK                                                        0x7FFFFFFFL
#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX__MM_APER_MASK                                                          0x80000000L
//BIF_BX_DEV0_EPF0_VF15_MM_DATA
#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA__SHIFT                                                         0x0
#define BIF_BX_DEV0_EPF0_VF15_MM_DATA__MM_DATA_MASK                                                           0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI
#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                0x0
#define BIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                  0xFFFFFFFFL


// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
//BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS
#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                     0x10
#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                       0x00010000L
//BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                     0x0
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                  0x1
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                     0x2
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                         0x3
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                               0x10
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                            0x11
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                               0x12
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                   0x13
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                       0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                       0x00000004L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                           0x00000008L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                 0x00010000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                              0x00020000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                 0x00040000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                     0x00080000L
//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK   0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT           0x0
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT         0x1
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT         0x8
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK             0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK           0x00000002L
#define BIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK           0x000FFF00L
//BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL
#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                         0x0
#define BIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                           0x00000001L
//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                   0x0
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                   0x1
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                   0x2
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                   0x3
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                   0x4
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                   0x5
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                   0x6
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                   0x7
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                   0x8
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                   0x9
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                 0xa
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                 0xb
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP0_MASK                                                     0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP1_MASK                                                     0x00000002L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP2_MASK                                                     0x00000004L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP3_MASK                                                     0x00000008L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP4_MASK                                                     0x00000010L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP5_MASK                                                     0x00000020L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP6_MASK                                                     0x00000040L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP7_MASK                                                     0x00000080L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP8_MASK                                                     0x00000100L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__CP9_MASK                                                     0x00000200L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                   0x00000400L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                   0x00000800L
//BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                  0x0
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                  0x1
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                  0x2
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                  0x3
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                  0x4
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                  0x5
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                  0x6
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                  0x7
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                  0x8
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                  0x9
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                0xa
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                0xb
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP0_MASK                                                    0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP1_MASK                                                    0x00000002L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP2_MASK                                                    0x00000004L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP3_MASK                                                    0x00000008L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP4_MASK                                                    0x00000010L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP5_MASK                                                    0x00000020L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP6_MASK                                                    0x00000040L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP7_MASK                                                    0x00000080L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP8_MASK                                                    0x00000100L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__CP9_MASK                                                    0x00000200L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                  0x00000400L
#define BIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                  0x00000800L
//BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING
#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                 0x0
#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                 0x1
#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                   0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                   0x00000002L
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                      0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                        0xFFFFFFFFL
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                           0x8
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                             0x9
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                               0x00000002L
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                             0x00000100L
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                               0x00000200L
//BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                           0x0
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                             0x1
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                               0x00000002L
//BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                           0x0
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                         0x1
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                              0x8
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                             0xf
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                              0x10
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                             0x17
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                               0x18
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                               0x19
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                             0x00000001L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                           0x00000002L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                0x00000F00L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                               0x00008000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                0x000F0000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                               0x00800000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                 0x01000000L
#define BIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                 0x02000000L


// addressBlock: syshub_mmreg_ind_syshubind
//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x0
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x1
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x2
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x3
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x4
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x5
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x6
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x7
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x10
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x11
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x12
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x13
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x14
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x15
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x16
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                  0x17
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                   0x1c
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT                                    0x1f
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000004L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000008L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000010L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000020L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000040L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00000080L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00010000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00020000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00040000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00080000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00100000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00200000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00400000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                    0x00800000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                     0x10000000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK                                      0x80000000L
//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT                                0x0
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK                                  0x0000FFFFL
//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT  0x0
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT  0x1
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT  0xf
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT  0x10
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT  0x11
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en_MASK  0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en_MASK  0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK  0x00008000L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK  0x00010000L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK  0x00020000L
//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT      0x0
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT      0x1
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT      0xf
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT      0x10
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT      0x11
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en_MASK        0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en_MASK        0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK        0x00008000L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK        0x00010000L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK        0x00020000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                   0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                   0x5
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                     0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                     0x0000001EL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                     0x000001E0L
//SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                   0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                   0x5
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                     0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                     0x0000001EL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                     0x000001E0L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
//SYSHUB_MMREG_IND_SYSHUB_CG_CNTL
#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT                                                  0x0
#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT                                          0x8
#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_EN_MASK                                                    0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER_MASK                                            0x0000FF00L
#define SYSHUB_MMREG_IND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER_MASK                                          0x00FF0000L
//SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT                                      0x0
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT                                      0x1
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT                                      0x2
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT                                      0x3
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT                                      0x4
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT                                      0x5
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT                                      0x6
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT                                      0x7
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT                                      0x8
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT                                      0x9
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT                                     0xa
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT                                     0xb
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT                                     0xc
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT                                     0xd
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT                                     0xe
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT                                     0xf
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT                                       0x10
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0_MASK                                        0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1_MASK                                        0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2_MASK                                        0x00000004L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3_MASK                                        0x00000008L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4_MASK                                        0x00000010L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5_MASK                                        0x00000020L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6_MASK                                        0x00000040L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7_MASK                                        0x00000080L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8_MASK                                        0x00000100L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9_MASK                                        0x00000200L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10_MASK                                       0x00000400L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11_MASK                                       0x00000800L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12_MASK                                       0x00001000L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13_MASK                                       0x00002000L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14_MASK                                       0x00004000L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15_MASK                                       0x00008000L
#define SYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF_MASK                                         0x00010000L
//SYSHUB_MMREG_IND_SYSHUB_HP_TIMER
#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT                                              0x0
#define SYSHUB_MMREG_IND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER_MASK                                                0xFFFFFFFFL
//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT                                0x0
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT                              0x1
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT                        0x2
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT                           0xa
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT                           0xb
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK__SHIFT                          0xc
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT                           0xd
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK                                  0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK                                0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK                          0x000003FCL
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK                             0x00000400L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK                             0x00000800L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REGS_DIS_SOCCLK_MASK                            0x00001000L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK                             0x00002000L
//SYSHUB_MMREG_IND_SYSHUB_SCRATCH
#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH__SHIFT                                                       0x0
#define SYSHUB_MMREG_IND_SYSHUB_SCRATCH__SCRATCH_MASK                                                         0xFFFFFFFFL
//SYSHUB_MMREG_IND_SYSHUB_CL_MASK
#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS__SHIFT                                              0x1
#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS__SHIFT                                                  0x2
#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1DRAM_MASK_DIS_MASK                                                0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_CL_MASK__MP1_MASK_DIS_MASK                                                    0x00000004L
//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x0
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x1
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x2
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x3
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x4
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x5
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x6
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x7
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x10
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x11
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x12
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x13
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x14
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x15
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x16
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                0x17
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                 0x1c
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT                                  0x1f
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000004L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000008L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000010L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000020L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000040L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00000080L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00010000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00020000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00040000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00080000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00100000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00200000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00400000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                  0x00800000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                   0x10000000L
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN_MASK                                    0x80000000L
//SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT                              0x0
#define SYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER_MASK                                0x0000FFFFL
//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT  0xf
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT  0x10
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en_MASK  0x00008000L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en_MASK  0x00010000L
//SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT    0xf
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT    0x10
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en_MASK      0x00008000L
#define SYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en_MASK      0x00010000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                   0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                   0x5
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                     0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                     0x0000001EL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                     0x000001E0L
//SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                   0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                   0x5
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                     0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                     0x0000001EL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                     0x000001E0L
//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                   0x1
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                 0x8
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                              0x9
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT                                        0x10
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT                                       0x18
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN_MASK                                     0x00000002L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                   0x00000100L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                0x00001E00L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT_MASK                                          0x00FF0000L
#define SYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT_MASK                                         0xFF000000L
//SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK__SHIFT                              0x0
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK__SHIFT                            0x1
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK__SHIFT                      0x2
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK__SHIFT                         0xa
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK__SHIFT                         0xb
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK__SHIFT                        0xc
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK                                0x00000001L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_MODE_SHUBCLK_MASK                              0x00000002L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HYSTERESIS_SHUBCLK_MASK                        0x000003FCL
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_HST_DIS_SHUBCLK_MASK                           0x00000400L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_DMA_DIS_SHUBCLK_MASK                           0x00000800L
#define SYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_REGS_DIS_SHUBCLK_MASK                          0x00001000L
//SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT                              0x0
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT                             0x1
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK                                0x00000001L
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK                               0x00000002L
//SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override__SHIFT                              0x0
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override__SHIFT                             0x1
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__read_iss_override_MASK                                0x00000001L
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS__write_iss_override_MASK                               0x00000002L
//SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override__SHIFT                              0x0
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override__SHIFT                             0x1
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__read_iss_override_MASK                                0x00000001L
#define SYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS__write_iss_override_MASK                               0x00000002L
//SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override__SHIFT                                     0x0
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override__SHIFT                                    0x1
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__read_iss_override_MASK                                       0x00000001L
#define SYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD__write_iss_override_MASK                                      0x00000002L
//SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS
#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT                              0x0
#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT                             0x1
#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK                                0x00000001L
#define SYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK                               0x00000002L

#endif
